Miniature field plate T-gate and method of fabricating the same

1. A method of fabricating a gate with a mini field plate for a transistor comprising:

forming a dielectric passivation layer over an epitaxy layer on a substrate;

coating the dielectric passivation layer with a first resist layer;

etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer;

removing the first resist layer; and

forming a tri-layer gate having a gate foot in the first opening, a gate neck extending from the gate foot, and a gate head extending from the gate neck, wherein the gate foot has a first width, wherein the gate neck has a second width that is wider than the first width, wherein the gate neck extends for a length over the dielectric passivation layer on both sides of the first opening, and wherein the gate head has a third width wider than the second width of the gate neck;

wherein forming the tri-layer gate comprises:

depositing a second resist layer on the dielectric passivation layer on either side of the first opening so that the second resist layer has a second opening in the second resist layer and so that the second opening is wider than the first opening;

depositing a third resist layer on the second resist layer on either side of the second opening so that the third resist layer has a third opening in the third resist layer and so that the third opening is wider than the second opening;

depositing a fourth resist layer on the third resist layer on either side of the third opening so that the fourth resist layer has a fourth opening in the fourth resist layer and so that the fourth opening is wider than the second opening and narrower than the third opening;

evaporating metal over the fourth resist layer so that the metal fills the first opening and the second opening and partially fills the third opening; and

removing the second, third and fourth resist layers.

2. The method of claim 1 further comprising:

forming low resistance ohmic contacts using a regrowth process.

3. The method of claim 1 wherein the substrate comprises GaN, sapphire, silicon carbide (SiC), silicon (Si), GaAs, InP, or InSb.

4. The method of claim 1 further comprising depositing a dielectric over the tri-layer gate.

5. The method of claim 1 wherein:

the first resist layer comprises an E-beam resist layer;

the second resist layer comprises an E-beam resist layer;

the third resist layer comprises an E-beam resist layer; and

the fourth resist layer comprises an E-beam resist layer.

6. The method of claim 1 wherein etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer comprises etching an E-beam defined gate foot pattern.

7. The method of claim 1 wherein the epitaxy layer comprises an AlGaN barrier layer.

8. The method of claim 1 wherein the transistor comprises a high electron mobility transistor.

9. The method of claim 1 wherein the gate neck extending for a length over the dielectric passivation layer on both sides of the first opening forms a first mini field plate on one side of the first opening and forms a second mini field plate on another side of the first opening.

10. The method of claim 9 :

wherein the gate head having a third width wider than the second width of the gate neck forms a third field plate on one side of the gate neck and forms a fourth field plate on another side of the gate neck;

wherein the third field plate is separated from the dielectric passivation layer by an air gap; and

wherein the fourth field plate is separated from the dielectric passivation layer by an air gap.

11. The method of claim 9 :

wherein the first mini field plate has a width of 10 nanometers to 40 nanometers; and

wherein the second mini field plate has a width of 10 nanometers to 40 nanometers.

12. The method of claim 9 :

wherein the height of the first mini field plate above the epitaxy layer is 5 nanometers to 75 nanometers; and

wherein the height of the second mini field plate above the epitaxy layer is 5 nanometers to 75 nanometers.

13. The method of claim 1 wherein the dielectric passivation layer has a thickness of 5 nanometers to 75 nanometers.

14. The method of claim 1 wherein the gate foot has a width of 40 nanometers or less.

15. A method of fabricating a gate with a mini field plate for a transistor comprising:

forming a dielectric passivation layer over an epitaxy layer on a substrate;

coating the dielectric passivation layer with a first resist layer;

etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer;

removing the first resist layer; and

forming a tri-layer gate having a gate foot in the first opening, a gate neck extending from the gate foot, and a gate head extending from the gate neck, wherein the gate foot has a first width, wherein the gate neck has a second width that is wider than the first width, wherein the gate neck extends for a length over the dielectric passivation layer on both sides of the first opening, and wherein the gate head has a third width wider than the second width of the gate neck;

wherein forming the tri-layer gate comprises:

depositing a second resist layer on the dielectric passivation layer on either side of the first opening so that the second resist layer has a second opening in the second resist layer and so that the second opening is wider than the first opening;

depositing a third resist layer on the second resist layer on either side of the second opening so that the third resist layer has a third opening in the third resist layer and so that the third opening is wider than the second opening;

depositing a fourth resist layer on the third resist layer on either side of the third opening so that the fourth resist layer has a fourth opening in the fourth resist layer and so that the fourth opening is wider than the second opening and narrower than the third opening;

evaporating metal over the fourth resist layer so that the metal fills the first opening and the second opening and partially fills the third opening; and

removing the second, third and fourth resist layers;

wherein the gate head forms a first field plate on one side of the gate neck and forms a second field plate on another side of the gate neck;

wherein the first field plate is separated from the dielectric passivation layer by a first air gap; and

wherein the second field plate is separated from the dielectric passivation layer by a second air gap.