Nanosheet device integrated with a FINFET transistor
View Patent ↗A semiconductor device includes a nanosheet device and a gate-all-around FIN-shaped (GAA-FIN) device. The nanosheet device includes n- and p-type field effect transistor (nFET and pFET) sections, each of which includes nanosheet stacks and work function metal (WFM). Each nanosheet stack includes lowermost and uppermost spacers, intermediate semiconductor layers and dielectric material surrounding the lowermost and uppermost spacers and the intermediate semiconductor layers. The WFM surrounds the nanosheet stacks and entirely fills suspension regions thereof. The GAA-FIN device includes nFET and pFET sections, each of which includes fin elements and WFM. Each fin element includes a lower spacer, a secondary intermediate layer of semiconductor material and dielectric material surrounding the lower spacer and the secondary intermediate layer of semiconductor material. The WFM surrounds each of the fin elements. A thickness of the WFM entirely filling the suspension regions exceeds a thickness of the WFM of the fin elements.
1. A semiconductor device comprising:
a nanosheet device comprising n- and p-type field effect transistor (nFET and pFET) sections, each of which comprises:
nanosheet stacks comprising lowermost and uppermost spacers, intermediate semiconductor layers and dielectric material surrounding the lowermost and uppermost spacers and the intermediate semiconductor layers; and
work function metal (WFM) surrounding the nano sheet stacks and entirely filling suspension regions thereof; and
a gate-all-around FIN-shaped (GAA-FIN) device comprising nFET and pFET sections, each of which comprises:
fin elements comprising a lower spacer, a secondary intermediate layer of semiconductor material and dielectric material surrounding the lower spacer and the secondary intermediate layer of semiconductor material; and
WFM surrounding the fin elements;
wherein a thickness of the WFM entirely filling suspension regions of the nanosheet stacks exceeds a thickness of the WFM surrounding the fin elements.
2. The semiconductor device according to claim 1 , wherein the nanosheet device comprises multiple nanosheet devices and the GAA-FIN device comprises multiple sets of the fin elements.
3. The semiconductor device according to claim 1 , wherein adjacent ones of the lowermost and uppermost spacers and the intermediate semiconductor layers are spaced at about ˜7 nm from one another.
4. The semiconductor device according to claim 1 , wherein a voltage threshold of the nanosheet device is lower than a voltage threshold of the GAA-FIN device.
5. The semiconductor device according to claim 1 , wherein the nanosheet device comprises an extremely-low voltage threshold (XLVT) device as compared to the GAA-FIN device.
6. The semiconductor device according to claim 1 , wherein:
the WFM of each nanosheet stack in the nFET section comprises first and second WFM and the WFM of each nanosheet stack in the pFET section comprises the second WFM;
the WFM of each fin element in nFET section comprises first and second WFM and the WFM of each fin element in the pFET section comprises the second WFM;
a thickness of the first WFM of each nanosheet stack exceeds a thickness of the first WFM of each fin element; and
a thickness of the second WFM in each nanosheet stack exceeds a thickness of the second WFM of each fin element.