Non-shared metal gate integration for scaled gate all around (GAA) transistors
Embodiments of the present invention are directed to processing methods and resulting structures for non-shared metal gate integrations for transistors. In a non-limiting embodiment of the invention, a first nanosheet stack is formed in a first region of a substrate and a second nanosheet stack is formed in a second region of the substrate. A first work function metal stack is formed around nanosheets in the first nanosheet stack and nanosheets in the second nanosheet stack, and a first sacrificial material is formed around the first work function metal stack. The first sacrificial material in the second nanosheet stack is replaced with a second sacrificial material and the first sacrificial material and the first work function metal stack in the first nanosheet stack are replaced with a second work function metal stack. The second sacrificial material in the second nanosheet stack is replaced with a third work function metal stack.
1 . A method for forming a semiconductor device, the method comprising:
forming a first nanosheet stack in a first region of a substrate and a second nanosheet stack in a second region of the substrate;
forming a first work function metal stack around one or more nanosheets in the first nanosheet stack and one or more nanosheets in the second nanosheet stack;
forming a first sacrificial material around the first work function metal stack in the first nanosheet stack and the first work function metal stack in the second nanosheet stack;
replacing the first sacrificial material in the second nanosheet stack with a second sacrificial material;
replacing the first sacrificial material and the first work function metal stack in the first nanosheet stack with a second work function metal stack; and
replacing the second sacrificial material in the second nanosheet stack with a third work function metal stack.
2 . The method of claim 1 , wherein the first work function metal stack pinches off a space between vertically adjacent nanosheets.
3 . The method of claim 1 , wherein a portion of the first sacrificial material pinches off a space between vertically adjacent nanosheets.
4 . The method of claim 1 , wherein replacing the first sacrificial material in the second nanosheet stack with the second sacrificial material comprises:
removing the first sacrificial material from the second nanosheet stack; and
forming the second sacrificial material around the first work function metal stack in the second nanosheet stack.
5 . The method of claim 1 , wherein replacing the first sacrificial material and the first work function metal stack in the first nanosheet stack with the second work function metal stack comprises:
removing the first sacrificial material and the first work function metal stack from the first nanosheet stack; and
forming the second work function metal stack around the one or more nanosheets in the first nanosheet stack.
6 . The method of claim 1 , wherein replacing the second sacrificial material in the second nanosheet stack with the third work function metal stack comprises:
removing the second sacrificial material from the second nanosheet stack; and
forming a third work function metal stack around the first work function metal stack in the second nanosheet stack.
7 . The method of claim 1 , wherein the first region of the substrate comprises an nFET region and the second region of the substrate comprises a pFET region.
8 . A method for forming a semiconductor device, the method comprising:
forming a first semiconductor structure in a first region of a substrate, the first semiconductor structure comprising a first gate in a non-shared metal gate integration; and
forming a second semiconductor structure in a second region of the substrate, the second semiconductor structure comprising a second gate in the non-shared metal gate integration;
wherein the second gate comprises a first work function metal stack and a third work function metal stack;
wherein the first gate comprises a second work function metal stack; and
wherein gate dielectrics are shared between the first gate and the second gate.
9 . The method of claim 8 , wherein the non-shared metal gate integration is structured such that no work function metal stacks are shared between the first semiconductor structure and the second semiconductor structure.
10 . The method of claim 8 , wherein the second work function metal stack in the first gate comprises a same material as one of the first work function metal stack and the third work function metal stack in the second gate, but the work function metals having a same material are not continuous across the first semiconductor structure and the second semiconductor structure.
11 . The method of claim 10 , wherein the first gate and the second gate comprises a continuous gate layout.
12 . The method of claim 8 , wherein the first semiconductor structure comprises a first nanosheet stack and the first region comprises an nFET region, and the second semiconductor structure comprises a second nanosheet stack and the second region comprises a pFET region.
13 . The method of claim 12 , wherein the first work function metal stack pinches off a space between vertically adjacent nanosheets in the second nanosheet stack.
14 . The method of claim 8 , wherein the first semiconductor structure comprises one or more semiconductor fins and the second semiconductor structure comprises one or more semiconductor fins.