Isolation structures of semiconductor devices
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.
1. A semiconductor structure, comprising:
a substrate;
a first vertical structure and a second vertical structure formed over the substrate;
a shallow trench isolation (STI) region between the first and second vertical structures; and
an isolation structure with a bottom portion embedded in the STI region, wherein the isolation structure comprises a center region and footing regions formed on opposite sides of the center region, each of the footing regions tapered towards the center region from a first end of the each footing region to a second end of the each footing region.
2. The semiconductor structure of claim 1 , wherein a bottom surface of each of the footing regions is substantially coplanar with a top surface of each of the first and second vertical structures.
3. The semiconductor structure of claim 1 , wherein the footing regions comprise a first footing region and a second footing region opposite to the first footing region, wherein a first separation between a first end of the first footing region and a first end of the second footing region is greater than a second separation between a second end of the first footing region and a second end of the second footing region.
4. The semiconductor structure of claim 1 , wherein a top surface of the center region is higher than a top surface of each of the first and second vertical structures.
5. The semiconductor structure of claim 1 , wherein the center region comprises sidewalls substantially perpendicular to the substrate, wherein the sidewalls are disposed between a top surface of the center region and the footing regions.
6. The semiconductor structure of claim 1 , further comprising a third vertical structure formed over the substrate and an other isolation structure disposed between the third vertical and second vertical structures, wherein:
a top surface of the other isolation structure is below a top surface of the isolation structure; and
the top surface of the other isolation structure is substantially coplanar with a top surface of each of the first, second, and third vertical structures.
7. The semiconductor structure of claim 1 , further comprising:
a first gate structure disposed on a portion of the first vertical structure; and
a second gate structure disposed on a portion of the second vertical structure, wherein the isolation structure is interposed between the first and second gate structures.
8. A field effect transistor (FET) structure, comprising:
a substrate;
a first vertical structure and a second vertical structure formed over the substrate, wherein each of the first and second vertical structures comprises a channel layer;
a shallow trench isolation (STI) region between the first and second vertical structures; and
an isolation structure with a bottom portion embedded in the STI region and comprising a first sidewall, a second sidewall, and a footing region between the first sidewall and the second sidewall, wherein:
the first and second sidewalls are between a top surface and a bottom surface of the isolation structure; and
the footing region is tapered from the second sidewall to the first sidewall.
9. The FET structure of claim 8 , further comprising:
a gate structure disposed over a portion of the first vertical structure, wherein the top surface of the isolation structure is above a top surface of the gate structure.
10. The FET structure of claim 9 , further comprising:
an other gate structure disposed over a portion of the second vertical structure, wherein the isolation structure is interposed between the gate structure and the other gate structure.
11. The FET structure of claim 9 , further comprising:
a third vertical structure comprising a channel layer; and
an other isolation structure disposed between the second and third vertical structures, wherein a top surface of the gate structure is above a top surface of the other isolation structure.
12. The FET structure of claim 9 , further comprising:
a third vertical structure comprising a channel layer; and
an other isolation structure disposed laterally adjacent to the third vertical structure, wherein a sidewall of the other isolation structure is a vertical surface that connects a top surface and a bottom surface of the other isolation structure, and wherein the top surface of the other isolation structure is above a top surface of the gate structure.
13. The FET structure of claim 8 , wherein the footing region comprises a first end and a second end above the first end, wherein a top surface of each of the first and second vertical structures is between the first end and the second end.
14. The FET structure of claim 13 , wherein the first end is laterally displaced from the second sidewall.
15. The FET structure of claim 13 , wherein the first end is substantially coplanar with the first and second vertical structures.
16. The FET structure of claim 8 , wherein a lower region comprising the second sidewall of the isolation structure and the footing region comprise different insulating materials.
17. A method for forming a semiconductor structure, comprising:
forming a first fin structure and a second fin structure over a substrate;
depositing a shallow trench isolation (STI) layer between the first and second fin structures;
forming an isolation structure on the STI layer, wherein the isolation structure comprises a first insulating layer and a second insulating layer disposed over the first insulating layer;
removing a portion of the STI layer such that a bottom portion of the isolation structure is embedded in the STI layer; and
removing a portion of the isolation structure to form a footing region tapering from a first sidewall of the isolation structure to a second sidewall of the isolation structure.
18. The method of claim 17 , wherein removing the portion of the isolation structure comprises:
forming a hard mask layer over a top surface of the isolation structure; and
selectively etching the second insulating layer using the hard mask layer.
19. The method of claim 18 , wherein selectively etching the second insulating layer comprises dry etching the second insulating layer with an etching selectivity of the second insulating layer to the first insulating layer of about 5 or greater.
20. The method of claim 17 , further comprising:
forming a first gate structure on a portion of the first fin structure; and
forming a second gate structure on a portion of the second fin structure, wherein the isolation structure is interposed between the first and second gate structures.