Isolation structures of semiconductor devices
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.
1. A semiconductor structure, comprising:
a first vertical structure and a second vertical structure on a substrate;
an isolation layer surrounding the first and second vertical structures;
an isolation structure on the isolation layer and between the first and second vertical structures, wherein a bottom portion of the isolation structure is embedded in the isolation layer and a top portion of the isolation structure comprises a footing region with sidewalls tapered from a bottom portion of the footing region to a top portion of the footing region; and
a gate structure comprising a first portion on the first vertical structure and a second portion on the second vertical structure, wherein the isolation structure is interposed between the first and second portions of the gate structure, and wherein the footing region is below a top surface of the gate structure.
2. The semiconductor structure of claim 1 , wherein the isolation structure comprises one or more layers of a low-k dielectric material, a high-k dielectric material, and combinations thereof.
3. The semiconductor structure of claim 1 , wherein a bottom surface of the footing region is substantially coplanar with top surfaces of the first and second vertical structures.
4. The semiconductor structure of claim 1 , further comprising an additional isolation structure extending into the isolation layer, wherein a top surface of the additional isolation structure is substantially coplanar with a bottom surface of the footing region.
5. The semiconductor structure of claim 4 , wherein the isolation structure and the additional isolation structure separates the first and second portions of the gate structure.
6. The semiconductor structure of claim 4 , wherein the isolation structure comprises a first dielectric material and the additional isolation structure comprises a second dielectric material different from the first dielectric material.
7. The semiconductor structure of claim 4 , wherein the additional isolation structure comprises silicon nitride and the isolation structure comprises silicon oxide.
8. The semiconductor structure of claim 1 , wherein the isolation structure comprises a bulk region and a liner surrounding the bulk region.
9. The semiconductor structure of claim 1 , further comprising a third vertical structure on the substrate and an additional isolation structure between the second and third vertical structures, wherein the additional isolation structure is buried in the second portion of the gate structure.
10. A semiconductor device, comprising:
a first channel structure and a second channel structure on a substrate;
a shallow trench isolation (STI) region between the first and second channel structures;
an isolation structure on the STI region and between the first and second channel structures, wherein the isolation structure extends into the STI region, wherein a top portion and a bottom portion of the isolation structure comprise different dielectric materials; and
a gate structure on the first and second channel structures, wherein the isolation structure extends above the gate structure and isolates the gate structure into a first portion on the first channel structure and a second portion on the second channel structure, and wherein a top surface of the bottom portion of the isolation structure is below a top surface of the gate structure.
11. The semiconductor device of claim 10 , wherein the isolation structure comprises one or more layers of a low-k dielectric material, a high-k dielectric material, and combinations thereof.
12. The semiconductor device of claim 10 , wherein a top surface of the isolation structure is above the top surface of the gate structure.
13. The semiconductor device of claim 10 , wherein the bottom portion of the isolation structure has footing regions.
14. The semiconductor device of claim 10 , wherein the top surface of the bottom portion is substantially coplanar with top surfaces of the first and second channel structures.
15. The semiconductor device of claim 10 , wherein the bottom portion comprises silicon oxide and the top portion comprises silicon nitride.
16. The semiconductor device of claim 10 , wherein the bottom portion comprises a bulk region and a liner surrounding the bulk region.
17. A semiconductor device, comprising:
first, second, and third channel structures on a substrate;
a shallow trench isolation (STI) region surrounding the first, second, and third channel structures;
a gate structure on the first, second, and third channel structures;
a first isolation structure between the first and second channel structures, wherein the first isolation structure extends above a top surface of the gate structure and separates the gate structure into a first portion and a second portion; and
a second isolation structure between the second and third channel structures, wherein a top surface of the second isolation structure is below the top surface of the second portion of the gate structure and a top surface of the first isolation structure.
18. The semiconductor device of claim 17 , wherein the first and second isolation structures comprise one or more layers of a low-k dielectric material, a high-k dielectric material, and combinations thereof.
19. The semiconductor device of claim 17 , wherein the top surface of the first isolation structure is above the top surface of the gate structure and a bottom surface of the first isolation structure is below a top surface of the STI region.
20. The semiconductor device of claim 17 , wherein the first isolation structure comprises a lower region and an upper region having footing regions.