Isolation structures of semiconductor devices

1. A method, comprising:

forming a first fin structure and a second fin structure on a substrate;

forming an isolation layer over the first and second fin structures;

forming a first insulating layer and a second insulating layer on the isolation layer and between the first and second fin structures; and

removing a portion of the isolation layer such that top surfaces of the isolation layer and the first insulating layer are below a bottom surface of the second insulating layer, wherein a bottom portion of the first insulating layer is embedded in a remaining portion of the isolation layer.

2. The method of claim 1 , wherein forming the isolation layer comprises:

depositing a liner and a dielectric layer, wherein the dielectric layer comprises one or more of an oxide material, a nitride material, and combinations thereof; and

performing a wet anneal process by annealing the liner and the dielectric layer in steam at a temperature between about 200° C. and about 700° C. for a period of time between about 30 min and about 120 min.

3. The method of claim 1 , wherein forming the first insulating layer comprises:

depositing one or more layers of a low-k dielectric material, a high-k dielectric material, and combinations thereof; and

etching back a portion of the one or more layers to form the first insulating layer, wherein the top surface of the first insulating layer is substantially coplanar with a top surface of each of the first and second fin structures.

4. The method of claim 1 , wherein forming the second insulating layer comprises:

depositing one or more dielectric layers; and

polishing the one or more dielectric layers to form the second insulating layer, wherein a top surface of the second insulating layer is substantially coplanar with the top surface of the isolation layer.

5. The method of claim 1 , further comprising:

forming one or more hard mask layers on each of the first and second fin structures; and

removing the one or more hard mask layers.

6. The method of claim 1 , wherein removing the portion of the isolation layer comprises etching the portion of the isolation layer at an etching rate between about 5 times and about 10 times greater than that of etching the first and second insulating layers.

7. The method of claim 1 , further comprising:

forming an organic mask layer and a photoresist mask layer on the second insulating layer; and

removing a portion of the second insulating layer exposed outside the organic mask layer and the photoresist mask layer to form a tapered region of the second insulating layer.

8. The method of claim 7 , wherein forming the organic mask layer comprises:

spin coating a polymer material over the second insulating layer, the remaining portion of the isolation layer, and the first and second fin structures; and

removing a portion of the polymer material exposed outside the photoresist mask layer.

9. The method of claim 1 , further comprising forming a first portion and a second portion of a gate structure, wherein the first and second insulating layers are interposed between the first and second portions of the gate structure.

10. The method of claim 1 , further comprising forming a first portion and a second portion of a gate structure, wherein a top surface of the second insulating layer is above a top surface of each of the first and second portions of the gate structure.

11. A method, comprising:

forming a shallow trench isolation (STI) structure to separate a first fin structure and a second fin structure disposed on a substrate;

forming an isolation structure between the first and second fin structures, wherein the isolation structure comprises a first insulating layer and a second insulating layer, and wherein a bottom portion of the first insulating layer is embedded in the STI structure; and

forming a first portion and a second portion of a gate structure, wherein the isolation structure is interposed between the first and second portions of the gate structure and a top surface of the isolation structure is above top surfaces of the first and second portions of the gate structure.

12. The method of claim 11 , wherein forming the STI structure comprises:

depositing a dielectric layer over the first and second fin structures, wherein the dielectric layer comprises one or more of an oxide material, a nitride material, and combinations thereof;

performing a wet anneal process by annealing the dielectric layer in steam at a temperature between about 200° C. and about 700° C. for a period of time between about 30 min and about 120 min; and

removing a portion of the dielectric layer.

13. The method of claim 12 , wherein removing the portion of the dielectric layer comprises etching the portion of the dielectric layer at an etching rate between about 5 times and about 10 times greater than that of etching the first and second insulating layers.

14. The method of claim 11 , wherein forming the isolation structure comprises:

depositing one or more layers of a low-k dielectric material, a high-k dielectric material, and combinations thereof; and

etching back a portion of the one or more layers to form the first insulating layer, wherein a top surface of the first insulating layer is substantially coplanar with a top surface of each of the first and second fin structures.

15. The method of claim 11 , further comprising:

forming an other isolation structure comprising a third insulating layer and a fourth insulating layer;

removing a portion of the second insulating layer to form a tapered region of the second insulating layer; and

removing the fourth insulating layer.

16. The method of claim 15 , further comprising:

spin coating a polymer material over the second and fourth insulating layers, the STI structure, and the first and second fin structures;

forming a photoresist mask layer on the polymer material spin coated over the second insulating layer; and

removing a portion of the polymer material exposed outside the photoresist mask layer.

17. A method, comprising:

forming first and second fin structures on a substrate;

depositing an isolation layer on the substrate and the first and second fin structures;

forming an isolation structure on the isolation layer and between the first and second fin structures, wherein a top surface of the isolation structure is above top surfaces of the first and second fin structures; and

removing a portion of the isolation layer on the first and second fin structures to form a shallow trench isolation (STI) structure, wherein a top surface of the STI structure is above a bottom surface of the isolation structure.

18. The method of claim 17 , wherein forming the isolation structure comprises:

forming a first insulating layer on the isolation layer between the first and second fin structures; and

forming a second insulating layer on the first insulating layer.

19. The method of claim 17 , wherein removing the portion of the isolation layer comprises etching the portion of the isolation layer at an etching rate greater than that of etching the isolation structure.

20. The method of claim 17 , further comprising forming a gate structure on the first and second fin structures, wherein:

the gate structure includes a first portion on the first fin structure and a second portion on the second fin structure;

the isolation structure electrically isolates the first portion and the second portion of the gate structure; and

the top surface of the isolation structure is above a top surface of each of the first and second portions of the gate structure.