IP Library › Granted Patent US 10,970,424
Granted Patent B2
US 10,970,424 · App. 16/776,869 · Granted Apr 6, 2021

Program execution device

Inventors: Hideki Matsushima (Osaka, JP); Teruto Hirota (Tokyo, JP); Yukie Shoda (Osaka, JP); Shunji Harada (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
G06F21/87G06F12/1408G06F21/10G06F21/14G06F21/52G06F21/53G06F21/57G06F21/74H04L9/3234H04L9/3247H04L63/105G06F2212/1052G06F2221/2153
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Quick Facts
Patent No.
US 10,970,424
App. No.
16/776,869
Granted
Apr 6, 2021
Kind
B2
Abstract

A program execution device capable of protecting a program against unauthorized analysis and alteration is provided. The program execution device includes an execution unit, a first protection unit, and a second protection unit. The execution unit executes a first program and a second program, and is connected with an external device that is capable of controlling the execution. The first protection unit disconnects the execution unit from the external device while the execution unit is executing the first program. The second protection unit protects the first program while the execution unit is executing the second program.

Claims (25)

1. An information processing device comprising: a hardware memory configured to load at least a program to be protected; and a controller configured to judge whether or not the program to be protected is tampered with, by executing a tamper detection program in a secure processing mode, wherein, in the secure processing mode, the controller is configured to prohibit an external device from accessing data in the hardware memory.

2. The information processing device according to claim 1 , wherein the tamper detection program is a program for detecting a tampering by using a digital signature.

3. The information processing device according to claim 1 , wherein the controller is configured to execute the program to be protected, when it is judged that the program to be protected has not been tampered with.

4. The information processing device according to claim 2 , wherein the controller is configured to execute the program to be protected, when it is judged that the program to be protected has not been tampered with.

5. The information processing device according to claim 1 , wherein the external device is a debugger.

6. The information processing device according to claim 1 , wherein the program includes program instructions.

7. The information processing device according to claim 6 , wherein the controller is configured to judge whether or not at least part of the program instructions of the program to be protected is tampered with, by executing the tamper detection program in the secure processing mode.

8. The information processing device according to claim 1 , wherein the controller is configured to change a processing mode, to the secure processing mode, from a normal processing mode which is a lower security level than the security level of the secure processing mode.

9. A method for operating an information processing device having a hardware memory loading at least one of a program to be protected and a processor executing the program, the method comprising:

judging by the processor whether or not the program to be protected is tampered with by using a tamper detection program in a secure processing mode,

wherein, in the secure processing mode, the processor is configured to prohibit an external device from accessing data in the hardware memory.

10. The method regarding to the claim 9 ,

wherein the tamper detection program is a program for detecting a tampering by using a digital signature.

11. The method regarding to the claim 9 ,

wherein the processor is configured to execute the program to be protected, when it is judged that the program to be protected has not been tampered with.

12. The method regarding to the claim 10 ,

wherein the processor is configured to execute the program to be protected, when it is judged that the program to be protected has not been tampered with.

13. The method regarding to the claim 9 ,

wherein the external device is a debugger.

14. The method regarding to the claim 9 ,

wherein the program includes program instructions.

15. The method regarding to the claim 14 ,

wherein the processor is configured to judge whether or not at least part of the program instructions of the program to be protected is tampered with, by executing the tamper detection program in the secure processing mode.

16. The method regarding to the claim 9 ,

wherein the processor is configured to change a processing mode, to the secure processing mode, from a normal processing mode which is a lower security level than the security level of the secure processing mode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2022
From: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 060361/0369 →
Priority Claims (1)
JP 2003-301554 · Aug 26, 2003 · national
Continuity (11)
Continuation 16393313 · Apr 24, 2019
Continuation 15964720 · Apr 27, 2018
Continuation 15719850 · Sep 29, 2017
Continuation 15348035 · Nov 10, 2016
Continuation 14941987 · Nov 16, 2015
Continuation 14483450 · Sep 11, 2014
Continuation 13952244 · Jul 26, 2013
Continuation 13441261 · Apr 6, 2012
Division 12367076 · Feb 6, 2009
Continuation 10569414
Related Publication 20200167509A1 · May 28, 2020