Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.
1. A semiconductor device comprising:
a first chip including:
a first pad,
a columnar portion provided above the first pad, and including at least a channel semiconductor layer that forms a memory cell array and extends in a first direction,
a plurality of bit lines provided below the columnar portion, and respectively extending in a second direction that crosses the first direction,
a first plug provided between a first bit line among the plurality of bit lines and the first pad, and electrically connecting the first bit line to the first pad, and
a second plug provided between the columnar portion and the first bit line, and electrically connecting the columnar portion to the first bit line; and
a second chip including:
a second pad provided below the first pad, and in contact with the first pad,
wherein the first bit line comprises a first portion in contact with the first plug, and a second portion in contact with the second plug, and the first portion is located in a position different from the second portion in the second direction.
2. The device of claim 1 , wherein
the memory cell array includes a plurality of electrode layers and a plurality of insulating layers that are alternately stacked, and
the columnar portion is provided in the plurality of electrode layers and the plurality of insulating layers.
3. The device of claim 2 , wherein the plurality of electrode layers function as word lines.
4. The device of claim 1 , wherein the first chip further comprises:
a first interconnection provided between the first pad and the first plug, electrically connected to the first plug, and extending in the second direction; and
a third plug provided between the first interconnection and the first pad, and electrically connecting the first interconnection to the first pad,
wherein the first interconnection comprises a third portion in contact with the first plug, and a fourth portion in contact with the third plug, and the third portion is located in a position different from the fourth portion in the second direction.
5. The device of claim 1 , wherein
the first bit line includes a linear portion that extends in a straight-line shape or in a curved-line shape, and
the first plug is provided on the linear portion.
6. The device of claim 5 , wherein
the linear portion includes at least a straight-line portion that extends in a straight-line shape, and a bent portion that is bent with respect to the straight-line portion, and
the first plug is provided on the straight-line portion.
7. The device of claim 5 , wherein
the linear portion includes at least a straight-line portion that extends in a straight-line shape, and a bent portion that is bent with respect to the straight-line portion, and
the first plug is provided on the bent portion.