IP Library › Granted Patent US 11,011,542
Granted Patent B2
US 11,011,542 · App. 16/786,273 · Granted May 18, 2021

Semiconductor device and method for manufacturing semiconductor device

Inventors: Shunpei Yamazaki (Setagaya, JP); Hajime Kimura (Atsugi, JP); Takanori Matsuzaki (Atsugi, JP); Kiyoshi Kato (Atsugi, JP); Satoru Okamoto (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/11582H01L27/1157H01L27/11565H01L27/11573H01L27/11575H01L29/24H01L29/513
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Quick Facts
Patent No.
US 11,011,542
App. No.
16/786,273
Granted
May 18, 2021
Kind
B2
Abstract

A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

Claims (38)

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating film;

forming a first conductive film over the first insulating film;

forming a second insulating film over the first conductive film;

processing the second insulating film, the first conductive film, and the first insulating film to form a first insulator comprising a first opening, a first conductor that is over the first insulator and comprises a second opening, and a second insulator that is over the first conductor and comprises a third opening;

processing the first insulator and the second insulator to make a diameter of the first opening and a diameter of the third opening larger than a diameter of the second opening;

forming a third insulator to be in contact with the first insulator, the first conductor, and the second insulator in the first opening, the second opening, and the third opening;

forming a first nitride comprising at least one of silicon and a metal element to be in contact with the third insulator;

processing the first nitride to form a second nitride having a sidewall surface substantially aligned with a sidewall surface of an inner wall of the third insulator in the first opening and the third opening; and

forming an oxide to be in contact with the third insulator and the second nitride in the first opening, the second opening, and the third opening.

2. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of:

performing heat treatment after forming the oxide.

3. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the third insulator has a stacked-layer structure comprising a fourth insulator, a fifth insulator, and a sixth insulator, and

wherein the third insulator having the stacked-layer structure is formed by forming the fourth insulator, forming the fifth insulator after the formation of the fourth insulator, and forming the sixth insulator after the formation of the fifth insulator.

4. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the oxide comprises In, an element M, and Zn, and

wherein M is Al, Ga, Y, or Sn.

5. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating film;

forming a first conductive film over the first insulating film;

forming a second insulating film over the first conductive film;

processing the second insulating film, the first conductive film, and the first insulating film to form a first insulator comprising a first opening, a first conductor that is over the first insulator and comprises a second opening, and a second insulator that is over the first conductor and comprises a third opening;

processing the first conductor to make a diameter of the second opening larger than a diameter of the first opening and a diameter of the third opening;

forming a third insulator to be in contact with the first insulator, the first conductor, and the second insulator in the first opening, the second opening, and the third opening;

forming an oxide to be in contact with the third insulator;

forming a third insulating film to be in contact with the oxide;

processing the third insulating film to form a fourth insulator having a sidewall surface substantially aligned with a sidewall surface of an inner wall of the oxide in the second opening; and

performing treatment for reducing resistance on part of the oxide using the fourth insulator as a mask.

6. The method for manufacturing a semiconductor device, according to claim 5 ,

wherein the treatment for reducing resistance is treatment for adding an element to the oxide.

7. The method for manufacturing a semiconductor device, according to claim 6 ,

wherein the element is at least one selected from argon, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, helium, neon, krypton, xenon, aluminum, ruthenium, titanium, tantalum, tungsten, chromium, and indium.

8. The method for manufacturing a semiconductor device, according to claim 5 ,

wherein the treatment for reducing resistance is any one of plasma treatment, ion implantation treatment, ion doping treatment, and reverse sputtering treatment.

9. The method for manufacturing a semiconductor device according to claim 5 ,

wherein the oxide comprises In, an element M, and Zn, and

wherein M is Al, Ga, Y, or Sn.

Priority Claims (2)
JP JP2017-119073 · Jun 16, 2017 · national
JP JP2017-132740 · Jul 6, 2017 · national
Continuity (2)
Division 16004890 · Jun 11, 2018
Related Publication 20200176473A1 · Jun 4, 2020
Cited By (3)
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