High power gallium nitride electronics using miscut substrates
A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.
1. A field effect transistor comprising:
a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction towards the <1 1 00> direction by an angle ranging between −0.3° and −0.6° and towards the <11 2 0> direction by an angle ranging between −0.1° and −0.2°;
a first epitaxial layer coupled to the III-V substrate;
a second epitaxial layer coupled to the first epitaxial layer;
one or more recessed regions extending into the second epitaxial layer, wherein each of the one or more recessed regions defines a sidewall surface in the second epitaxial layer and a lateral surface, wherein a doped region extends into the sidewall surface and the lateral surface;
a drain contact in electrical contact with the III-V substrate;
a source contact in electrical contact with the second epitaxial layer; and
a gate contact in electrical contact with the doped region.
2. The field effect transistor of claim 1 wherein the III-V substrate comprises an n-type GaN substrate.
3. The field effect transistor of claim 1 wherein the first epitaxial layer comprises an n-type GaN epitaxial layer and the second epitaxial layer comprises an n-type GaN epitaxial layer.
4. The field effect transistor of claim 1 wherein the doped region comprises a diffused region.
5. The field effect transistor of claim 1 wherein the doped region comprises zinc.
6. The field effect transistor of claim 1 wherein the doped region comprises magnesium.
7. The field effect transistor of claim 1 wherein the doped region comprises beryllium.
8. The field effect transistor of claim 1 wherein the doped region comprises calcium.
9. The field effect transistor of claim 1 wherein the first epitaxial layer has a thickness greater than 5 μm.
10. The field effect transistor of claim 1 wherein a dopant concentration in the first epitaxial layer varies as a function of a thickness of the first epitaxial layer.
11. The field effect transistor of claim 1 wherein a dopant concentration in the second epitaxial layer varies as a function of a thickness of the second epitaxial layer.
12. The field effect transistor of claim 1 wherein the doped region extends into the second epitaxial layer by a distance between about 1 nm and about 1 μm.
13. The field effect transistor of claim 12 wherein the lateral surface is disposed in the first epitaxial layer.
14. The field effect transistor of claim 13 wherein the doped region extends into the first epitaxial layer by a distance between about 1 nm and about 1 μm.
15. The field effect transistor of claim 1 wherein the lateral surface is substantially orthogonal to a growth direction of the first epitaxial layer.
16. The field effect transistor of claim 1 wherein the sidewall surface is substantially parallel to a growth direction of the second epitaxial layer.
17. The field effect transistor of claim 1 wherein the lateral surface is disposed in the second epitaxial layer.
18. The field effect transistor of claim 1 further comprising an isolation region disposed laterally to the second epitaxial layer.