Junction field effect transistor (JFET) structure and methods to form same
A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.
1. A junction field effect transistor (JFET) structure, comprising:
a semiconductor layer including a channel region between a source region and a drain region;
a doped polysilicon gate over the channel region of the semiconductor layer, the doped polysilicon gate having a first doping type, wherein the doped polysilicon gate includes a first sidewall and a second sidewall opposite the first sidewall;
a raised epitaxial source on the source region of the semiconductor layer and adjacent the first sidewall of the doped polysilicon gate, the raised epitaxial source having a second doping type opposite the first doping type;
a raised epitaxial drain on the drain region of the semiconductor layer and adjacent the second sidewall of the doped polysilicon gate, the raised epitaxial drain having the second doping type;
a doped semiconductor region within the channel region of the semiconductor layer and extending from the source region to the drain region; and
a non-conductive portion of the semiconductor layer within the channel region separating the doped semiconductor region from the doped polysilicon gate.
2. The JFET structure of claim 1 , wherein the doped semiconductor region includes silicon (Si), and wherein the raised epitaxial source and the raised epitaxial drain each include silicon germanium (SiGe).
3. The JFET structure of claim 1 , further comprising a dopant diffusion barrier vertically between the non-conductive portion of the semiconductor layer and a bottom surface of the doped polysilicon gate.
4. The JFET structure of claim 1 , wherein the dopant diffusion barrier includes an oxide material having a thickness of at most approximately one monolayer.
5. The JFET structure of claim 1 , further comprising a first spacer directly horizontally between the first sidewall of the doped polysilicon gate and the raised epitaxial source, and a second spacer directly horizontally between the second sidewall of the doped polysilicon gate and the raised epitaxial drain.
6. The JFET structure of claim 1 , wherein a bottom surface of the doped polysilicon gate is above a bottom surface of the raised epitaxial source and a bottom surface of the raised epitaxial drain.
7. The JFET structure of claim 1 , further comprising:
a trench isolation region having a first sidewall directly horizontally adjacent to the semiconductor layer; and
a non-JFET transistor directly horizontally adjacent to a second sidewall of the trench isolation region, opposite the first sidewall of the trench isolation region.