Systems and methods for program verification on a memory system
A method for memory program verification includes performing a write operation on memory cells of a memory device. The method also includes identifying memory strings associated with respective memory cells of the memory cells. The method also includes identifying a first memory string of the memory strings. The method also includes disabling a portion of a write verification for the first memory string. The method also includes enabling the portion of the write verification for other memory strings of the memory strings. The method also includes performing at least the portion of the write verification operation on write verification enabled memory strings.
1. A method for memory program verification, the method comprising:
performing a write operation on memory cells of a memory device;
identifying memory strings associated with respective memory cells of the memory cells;
identifying a first memory string of the memory strings;
disabling a portion of a write verification for the first memory string, the portion of the write verification causing a verification voltage spike;
enabling the portion of the write verification for other memory strings of the memory strings; and
performing at least the portion of the write verification operation on memory strings having the portion of the write verification enabled.
2. The method of claim 1 , wherein the first memory string includes a memory string programmed first during performance of the write operation.
3. The method of claim 1 , wherein performing at least the portion of the write verification operation includes:
applying the verification voltage spike to the memory strings having the portion of the write verification enabled; and
skipping application of the verification voltage spike to the first memory string.
4. The method of claim 1 , wherein performing the portion of the write verification operation includes equalizing channel potential of the memory device.
5. The method of claim 1 , wherein the memory device includes a single level cell memory device.
6. The method of claim 1 , wherein the memory device includes a multiple level cell memory device.
7. The method of claim 1 , wherein the memory device includes a triple level cell memory device.
8. The method of claim 1 , wherein the memory device includes a quad level cell memory device.
9. A controller comprising:
a bus interface in communication with at least one memory block of a memory device; and
a processor configured to:
perform a write operation on memory cells of the at least one memory block;
identify memory strings associated with respective memory cells of the memory cells;
identify a first memory string of the memory strings;
disable a portion of a write verification for the first memory string, the portion of the write verification causing a verification voltage spike;
enable the portion of the write verification for other memory strings of the memory strings; and
perform at least the portion of the write verification operation on memory strings having the portion of the write verification enabled.
10. The controller of claim 9 , wherein the first memory string includes a memory string programmed first during performance of the write operation.
11. The controller of claim 9 , wherein the instructions further cause the processor to perform at least the portion of the write verification operation by:
applying the verification voltage spike to the memory strings having the portion of the write verification enabled, and
skipping application of the verification voltage spike to the first memory string.
12. The controller of claim 9 , wherein the memory cells include one bit.
13. The controller of claim 9 , wherein the memory cells include two bits.
14. The controller of claim 9 , wherein the memory cells include three bits.
15. The controller of claim 9 , wherein the memory cells include four bits.
16. A method for memory program verification, the method comprising:
performing a write operation on memory cells of a memory device;
identifying memory strings associated with respective memory cells of the memory cells;
identifying a first memory string of the memory strings, the first memory string including a memory string of the memory strings to be programmed first during performance of the write operation;
in response to completion of performance of the write operation on the first memory string, skipping performance of a portion of a write verification operation on the first memory string, the portion of the write verification causing a verification voltage spike; and
performing, in response to completion of performance of the write operation on subsequently programmed memory strings, at least the portion of the write verification operation on the respective subsequently programmed memory strings of the memory strings.
17. The method of claim 16 , wherein the memory device includes a single level cell memory device.
18. The method of claim 16 , wherein the memory device includes a multiple level cell memory device.
19. The method of claim 16 , wherein the memory device includes a triple level cell memory device.
20. The method of claim 16 , wherein the memory device includes a quad level cell memory device.