Method to produce a multi-level semiconductor memory device and structure
A method to process a 3D device, the method including: providing a first substrate including a first level including a first single crystal silicon layer and a plurality of first transistors; providing a second substrate including a second level including a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer; forming a plurality of third transistors including the third single crystal silicon layer; forming a plurality of metal layers interconnecting the plurality of third transistors; and then performing a hybrid bonding of the second level onto the first level.
1. A method of making a 3D multilayer semiconductor device, the method comprising:
providing a first substrate comprising a first level comprising a first single crystal silicon layer and a plurality of first transistors;
providing a second substrate comprising a second level comprising a second single crystal silicon layer;
performing an epitaxial growth of a SiGe layer on top of said second single crystal silicon layer;
performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer;
forming a plurality of second transistors within said third single crystal silicon layer;
forming a plurality of metal layers interconnecting said plurality of second transistors; and then
performing a hybrid bonding of said second level onto said first level,
wherein performing said hybrid bonding comprises making a plurality of oxide-to-oxide bonds and metal-to-metal bonds on a same surface.
2. The method according to claim 1 , further comprising:
after said bonding removing said second single crystal silicon layer.
3. The method according to claim 1 , further comprising:
prior to said bonding, etching at least a portion of said SiGe layer.
4. The method according to claim 1 ,
wherein said first level comprises an array of memory cells.
5. The method according to claim 1 , further comprising:
forming memory control circuits,
wherein said memory control circuits comprise said plurality of second transistors.
6. The method according to claim 1 ,
wherein said bonding is a compression type bonding.
7. The method according to claim 1 , further comprising:
processing a through layer via substantially through said third single crystal silicon layer.
8. A method of making a 3D multilayer semiconductor device, the method comprising:
providing a first substrate comprising a first level,
wherein said first level comprises a first single crystal silicon layer and a plurality of first transistors,
wherein said plurality of said first transistors are formed into said first single crystal silicon layer;
forming an array of memory cells at least on said first level,
wherein each of said memory cells comprises at least one of said plurality of first transistors;
providing a second substrate comprising a second level,
wherein said second level comprises a second single crystal silicon layer and a plurality of second transistors, and
wherein said plurality of said second transistors are formed into said second single crystal silicon layer;
forming memory control circuits on said second level,
wherein said memory control circuits comprise a portion of said plurality of second transistors; and then
performing a hybrid bonding of said second level onto said first level,
wherein performing said hybrid bonding comprises making a plurality of oxide-to-oxide bonds and metal-to-metal bonds on a same surface, and
wherein said second level further comprises a SiGe layer.
9. A method of making a 3D multilayer semiconductor device, the method comprising:
providing a first substrate comprising a first level,
wherein said first level comprises a first single crystal silicon layer and a plurality of first transistors,
wherein said plurality of said first transistors are formed into said first single crystal silicon layer;
forming an array of memory cells at least on said first level,
wherein each of said memory cells comprises at least one of said plurality of first transistors;
providing a second substrate comprising a second level,
wherein said second level comprises a second single crystal silicon layer and a plurality of second transistors, and
wherein said plurality of said second transistors are formed into said second single crystal silicon layer;
forming memory control circuits on said second level,
wherein said memory control circuits comprise said second transistors; and then performing a hybrid bonding of said second level onto said first level,
wherein said performing hybrid bonding comprises making a plurality of oxide-to-oxide bonds and metal-to-metal bonds on a same surface, and
wherein said second level comprises a cut layer, and
after said hybrid bonding, removing at least a portion of said second single crystal silicon layer,
wherein said removing utilizes said cut layer.
10. The method according to claim 8 , further comprising:
after said bonding removing a portion of said second single crystal silicon layer.
11. The method according to claim 8 , further comprising:
etching at least a portion of said SiGe layer.
12. The method according to claim 8 , further comprising:
a plurality of memory control line connections,
wherein at least one of said connections comprises at least one of said metal to metal bonds.
13. The method according to claim 8 ,
wherein said memory array comprises a plurality of independently controlled sub-arrays.
14. The method according to claim 8 ,
wherein said memory array comprises a 3D memory array.
15. The method according to claim 8 , further comprising:
processing a through layer via through said second single crystal silicon layer.
16. The method according to claim 9 ,
wherein said cut layer comprises a SiGe layer.
17. The method according to claim 9 , further comprising:
a plurality of memory control line connections,
wherein at least one of said connections comprises at least one of said metal to metal bonds.
18. The method according to claim 9 ,
wherein said memory array comprises a plurality of independently controlled sub-arrays.
19. The method according to claim 9 ,
wherein said memory array comprises a 3D memory array.
20. The method according to claim 9 , further comprising:
processing a through layer via through said second single crystal silicon layer.