IP Library Granted Patent US 11,569,140
Granted Patent B2
US 11,569,140 · App. 16/799,026 · Granted Jan 31, 2023

Semiconductor package with elastic coupler and related methods

Inventors: Yusheng Lin (Phoenix, AZ); Chee Hiong Chew (Seremban, MY); Francis J. Carney (Mesa, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/055H01L21/50H01L23/041H01L23/053H01L23/057H01L23/10H01L23/492H01L23/49811H01L23/49844H01L23/49861H01L23/50H01L24/72H01L25/072H01R4/489H01R4/4863H01L23/4006H01L24/45H01L24/48H01L25/18H01L2224/0401H01L2224/04034H01L2224/04042H01L2224/05553H01L2224/0603H01L2224/06181H01L2224/16227H01L2224/32225H01L2224/33181H01L2224/45124H01L2224/48137H01L2224/48139H01L2224/48227H01L2224/72H01L2224/73265H01L2224/81815H01L2924/13055H01L2924/13091H01L2924/19107
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Quick Facts
Patent No.
US 11,569,140
App. No.
16/799,026
Granted
Jan 31, 2023
Kind
B2
Abstract

Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

Claims (36)

1. A pin for a semiconductor package, comprising:

a shaft comprising an upper portion configured to couple with a housing and comprising a lower portion;

wherein the lower portion comprises a reversibly elastically deformable portion;

wherein the reversibly elastically deformable lower portion is configured to be located between the housing and a substrate;

wherein the upper portion is configured to extend through the housing; and

wherein the reversibly elastically deformable portion is configured to compress when the housing is coupled over the substrate.

2. The pin of claim 1 , wherein a base of the pin is coupled to the substrate with a spring.

3. The pin of claim 1 , wherein the pin is configured to at least temporarily fixedly couple in a top of the housing and is configured to be coupled with the substrate by lowering the housing towards the substrate.

4. The pin of claim 1 , wherein the reversibly elastically deformable lower portion comprises a spring.

5. The pin of claim 1 , wherein the reversibly elastically deformable lower portion is configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the lower end of pin when the housing is lowered to be coupled to the substrate.

6. The pin of claim 1 , wherein the pin is configured to couple to a connection trace coupled to a semiconductor die, wherein the semiconductor die is at least partially enclosed within a cavity of the housing.

7. The pin of claim 1 , wherein the upper portion is configured to be molded into and fixedly coupled to the housing.

8. The pin of claim 1 , wherein the pin is configured to directly couple to the substrate through a solderless connection.

9. A pin for a semiconductor package, comprising:

a shaft comprising an upper portion configured to couple with a housing and comprising a lower portion;

wherein the lower portion comprises a reversibly elastically deformable portion;

wherein the reversibly elastically deformable portion is configured to be located between the housing and a substrate;

wherein the upper portion is configured to extend through the housing;

wherein the reversibly elastically deformable portion is configured to compress when the housing is coupled over the substrate; and

wherein the pin is configured to be coupled with the substrate by lowering the housing towards the substrate.

10. The pin of claim 9 , wherein a base of the pin is configured to couple to the substrate with a spring.

11. The pin of claim 9 , wherein the reversibly elastically deformable portion comprises a spring.

12. The pin of claim 9 , wherein the pin is configured to couple to a connection trace coupled to a semiconductor die, wherein the semiconductor die is at least partially enclosed within a cavity of the housing.

13. The pin of claim 9 , wherein the lower portion is configured to directly couple to the substrate through a solderless connection.

14. A pin for a semiconductor package, comprising:

a shaft comprising an upper portion configured to couple with a housing and comprising a lower portion;

wherein the lower portion comprises a spring;

wherein the spring biases the upper portion of the pin towards the housing;

wherein the shaft is configured to extend through the housing; and

wherein the spring is configured to be located between the housing and a substrate.

15. The pin of claim 14 , wherein the spring comprises a coil spring.

16. The pin of claim 14 , wherein the spring is configured to be compressed along a direction substantially parallel with the shaft of the pin.

17. The pin of claim 14 , wherein the spring is configured to prevent a contact surface of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered towards the substrate.

18. The pin of claim 14 , wherein the spring is a helical spring.

19. The pin of claim 14 , wherein the pin is configured to be compressed when the housing is placed over the substrate.

20. The pin of claim 14 , wherein the lower portion is configured to directly couple to the substrate through a solderless connection.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 052656, FRAME 0842 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064080/0149 →
SECURITY INTEREST Recorded May 13, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 052656/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2020
From: LIN, YUSHENG; CARNEY, FRANCIS J.; CHEW, CHEE HIONG
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 051904/0624 →
Continuity (5)
Continuation 16396904 · Apr 29, 2019
Continuation 15630112 · Jun 22, 2017
Continuation 15230076 · Aug 5, 2016
Division 14626758 · Feb 19, 2015
Related Publication 20200194322A1 · Jun 18, 2020