Package and manufacturing method thereof
A package includes a first die, a second die, an encapsulant, and a redistribution structure. The first die has a first capacitor embedded therein. The second die has a second capacitor embedded therein. The second die is stacked on the first die. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die. The redistribution structure is disposed on the second die and the encapsulant.
1. A package, comprising:
a first die, comprising:
a first semiconductor substrate;
a first interconnection structure disposed on the first semiconductor substrate, wherein the first interconnection structure comprises a first capacitor embedded therein; and
a first bonding layer disposed over the first interconnection structure;
a second die stacked on the first die, comprising:
a second semiconductor substrate;
a second interconnection structure disposed on the second semiconductor substrate, wherein the second interconnection structure comprises a second capacitor embedded therein; and
a second bonding layer disposed over the second interconnection structure, wherein the first capacitor is electrically connected to the second capacitor through the first bonding layer and the second bonding layer; and
an encapsulant laterally encapsulating the second die.
2. The package of claim 1 , wherein the first die further comprises:
a passivation layer sandwiched between the first interconnection structure and the first bonding layer;
conductive pads embedded in the passivation layer; and
bonding vias penetrating through the passivation layer to connect the first bonding layer and the first capacitor.
3. The package of claim 2 , wherein the first capacitor comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order, one of the bonding vias is directly in contact with the top metal layer, and another one of the bonding vias is directly in contact with the bottom metal layer.
4. The package of claim 3 , wherein the first interconnection structure comprises dielectric layers and conductive patterns embedded in the dielectric layers, and a material of the dielectric layers of the first interconnection structure is different from a material of the insulating layer of the first capacitor.
5. The package of claim 2 , wherein the first capacitor comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order, the insulating layer and the top metal layer comprise an opening exposing the bottom metal layer, and at least one of the bonding vias extends into the opening to contact the bottom metal layer.
6. The package of claim 2 , wherein the first die further comprises a third capacitor embedded in the passivation layer, and the third capacitor is electrically connected to the first capacitor and the second capacitor.
7. The package of claim 1 , further comprising:
a redistribution structure disposed on the second die and the encapsulant; and
through insulating vias (TIV) electrically connecting the first die and the redistribution structure.
8. The package of claim 7 , wherein the second die further comprises through semiconductor vias (TSV) penetrating through the second semiconductor substrate, and the TSVs electrically connect the second interconnection structure and the redistribution structure.
9. A package, comprising:
a first die, comprising:
a first semiconductor substrate;
a first interconnection structure disposed on the first semiconductor substrate; and
first bonding pads and first bonding vias over the first semiconductor substrate;
a second die stacked on the first die, comprising:
a second semiconductor substrate;
a second interconnection structure disposed on the second semiconductor substrate; and
second bonding pads and second bonding vias over the second semiconductor substrate;
a passive device, comprising a first portion and a second portion electrically connected to the first portion, wherein the first portion is embedded in the first interconnection structure, the second portion is embedded in the second interconnection structure, the first bonding vias connect the first bonding pads and the first portion, the second bonding vias connect the second bonding pads and the second portion, the first portion is electrically connected to the second portion through the first bonding ads and the second bonding pads, the first portion comprises a bottom metal layer, an insulating layer, and a top metal layer stacked in sequential order, one of the first bonding vias is directly in contact with the top metal layer, and another one of the first bonding vias is directly in contact with the bottom metal layer; and
an encapsulant laterally encapsulating the second die.
10. The package of claim 9 , wherein the first interconnection structure comprises dielectric layers and conductive patterns embedded in the dielectric layers, and a material of the dielectric layers of the first interconnection structure is different from a material of the insulating layer.
11. The package of claim 9 , wherein the insulating layer and the top metal layer comprise an opening exposing the bottom metal layer, and the another one of the first bonding vias extends into the opening to contact the bottom metal layer.
12. The package of claim 9 , further comprising:
a redistribution structure disposed on the second die and the encapsulant;
through insulating vias (TIV) penetrating through the encapsulant, wherein the TIVs electrically connect the first die and the redistribution structure.
13. The package of claim 9 , wherein sidewalls of each first bonding pad are aligned with sidewalls of the corresponding second bonding pad.
14. The package of claim 12 , wherein the first die further comprises third bonding pads levelled with the first bonding pads, and the TIVs are in direct contact with the third bonding pads.