Semiconductor device including nonvolatile memory device and logic device and manufacturing method of semiconductor device including nonvolatile memory device and logic device

1. A semiconductor device, comprising:

a nonvolatile memory device, comprising:

a first well region formed in a substrate;

a tunneling gate insulator formed on the first well region;

a floating gate formed on the tunneling gate insulator;

a thick dielectric pattern formed on sidewalls of the floating gate;

a control gate insulator formed on the substrate;

a control gate disposed on the thick dielectric pattern formed on sidewalls of the floating gate to enclose the floating gate, and formed on the control gate insulator; and

a first source region and a first drain region formed on opposite sides of the control gate, respectively; and

a first logic device, comprising:

a first logic well region formed in the substrate;

a first logic gate insulator formed on the first logic well region;

a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device; and

a first logic source region and a first logic drain region formed on opposite sides of the first logic gate, respectively.

2. The semiconductor device of claim 1 , further comprising:

a second logic device, comprising:

a second logic well region formed in the substrate;

a second logic gate insulator formed on the second logic well region;

a second logic gate formed on the second logic gate insulator, wherein the second logic gate comprises substantially a same material as the material of the control gate of the nonvolatile memory device; and

a second logic source region and a second logic drain region formed on opposite sides of the second logic gate, respectively,

wherein a depth of the first logic well region below the first logic gate is shallower than a depth of the first logic well region below the first logic source region and the first logic drain region, and

wherein a depth of the second logic well region below the second logic gate is shallower than a depth of the second logic well region below the second logic source region and the second logic drain region.

3. The semiconductor device of claim 1 , wherein the control gate insulator has a thickness greater than a thickness of the first logic insulator and greater than a thickness of the second logic gate insulator.

4. The semiconductor device of claim 1 , wherein the nonvolatile memory device further comprises:

a hard mask pattern comprising a first insulating layer and a second insulating layer different from the first insulating layer, and formed on the floating gate;

control gate spacers formed on sidewalls of the control gate; and

a first silicide layer formed on the control gate.

5. The semiconductor device of claim 1 , wherein the nonvolatile memory device further comprises:

a deep well region formed below the first well region, wherein the deep well region has a depth greater than a depth of the first logic well region; and

a lightly-doped drain (LDD) region formed in the first well region, wherein the LDD region has a depth greater than a depth of the first source region and greater than a depth of the first drain region.

6. The semiconductor device of claim 1 , wherein the control gate has a height greater than a height of the first logic gate with respect to a top surface of the substrate.

7. A semiconductor device, comprising:

a substrate having a cell region and a logic region, wherein a nonvolatile memory device is formed on the cell region and a logic device is formed on the logic region;

a first well region formed in the cell region of the substrate;

a tunneling gate insulator formed on the first well region;

a floating gate formed on the tunneling gate insulator;

a thick dielectric pattern formed on sidewalls of the floating gate;

a control gate insulator formed on the cell region;

a first logic gate insulator formed on the logic region;

a control gate disposed on the thick dielectric pattern formed on sidewalls of the floating gate to enclose the floating gate, and formed on the control gate insulator;

a first logic gate formed on the first logic gate insulator;

a first logic well region formed in the logic region;

control gate spacers formed on each sidewall of the control gate and first logic gate spacers formed on each sidewall of the first logic gate;

a first source region and a first drain region formed on opposite sides of the control gate, respectively; and

a first logic source region and a first logic drain region formed on opposite sides of the first logic gate, respectively.

8. The semiconductor device of claim 7 , wherein the first logic well region below the first logic gate has a depth shallower than a depth of the first logic well region below the first logic source region and the first logic drain region.

9. The semiconductor device of claim 7 , wherein the first logic gate and the control gate are simultaneously formed.

10. The semiconductor device of claim 7 , further comprising:

a deep well region formed in the substrate, wherein the deep well region encloses the first well region; and

a lightly doped drain (LDD) region formed in the first well region, wherein the LDD region encloses the first source region and the first drain region.

11. The semiconductor device of claim 7 , further comprising:

a second logic well region formed in the logic region;

a second logic source region and a second logic drain region on opposite sides of the second logic gate, respectively; and

wherein the second logic well region below the second logic gate has a depth shallower than a depth of the second logic well region below the second logic source region and the second logic drain region.

12. The semiconductor device of claim 4 , wherein the first insulating layer of the hard mask pattern is a silicon oxide layer, and the second insulating layer of the hard mask pattern is a silicon nitride layer.

13. The semiconductor device of claim 1 , wherein the thick dielectric pattern comprises first, second and third insulating layers, and formed between the floating gate and the control gate, and

wherein the first insulating layer of the thick dielectric pattern is a first silicon oxide layer, the second insulating layer of the thick dielectric pattern is a silicon nitride layer, and the third insulating layer of the thick dielectric pattern is a second silicon oxide layer sequentially disposed in that order.

14. The semiconductor device of claim 1 , wherein the floating gate has a rectangular shape with rounded corners, and is inclined to the right or left with respect to a vertical axis in a plan view.

15. The semiconductor device of claim 7 , wherein the floating gate has a rectangular shape with rounded corners, and is inclined to the right or left with respect to a vertical axis in a plan view.

16. The semiconductor device of claim 1 , wherein the control gate has a rectangular shape with rounded corners, and is inclined to the right or left with respect to a vertical axis in a plan view.