Programmable resistance memory on thin film transistor technology
Programmable resistive memory can be fabricated with a non-single-crystalline silicon formed on a flexible substrate. The non-single-crystalline silicon can be amorphous silicon, low-temperature polysilicon (LTPS), organic semiconductor, or metal oxide semiconductor. The flexible substrate can be glass, plastics, paper, metal, paper, or any kinds of flexible film. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a silicon, polysilicon, organic or metal oxide electrode. The selector in a programmable resistive memory can be a MOS or diode with top gate, bottom gate, inverted, staggered, or coplanar structures.
1. A programmable resistive memory, comprising:
a plurality of programmable resistive cells, at least one of the cells comprising:
a programmable resistive element (PRE) having one end coupled to a first supply voltage line;
a selector having at least a first active region and a second active region, where the first active region having a first type of dopant and a second active region having a first or a second type of dopant, the first active region providing a first terminal of the selector, the second active region providing a second terminal of the selector, both the first and second active regions built on a non-single-crystal-silicon semiconductor film on an insulator substrate, the first active region coupled to the PRE and the second active region coupled to a second supply voltage line; and
a gate fabricated on the layer of non-single-crystalline-silicon semiconductor with a sandwich of dielectric in between; the gate coupled to a third supply voltage line that can control conductivity between the first and the second active region, and
wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or the third supply voltage lines to thereby change its logic state.
2. A programmable resistive memory as recited in claim 1 , wherein the insulator substrate comprises a glass, plastic, paper, metal, cellular, or any kind of flexible film.
3. A programmable resistive memory as recited in claim 1 , wherein the non-single-crystal-silicon semiconductor film consists of at least one of amorphous silicon, polycrystalline silicon (polysilicon), or silicon-germanium.
4. A programmable resistive memory as recited in claim 1 , wherein the non-single-crystal-silicon semiconductor film consists of at least one of organic or metal oxide semiconductor.
5. A programmable resistive memory as recited in claim 1 , wherein the programmable resistive element consists of at least one of a phase-change film in PCRAM or resistive thin film in RRAM.
6. A programmable resistive memory as recited in claim 1 , wherein the programmable resistive element consists of at least one of a magnetic tunnel junction (MTJ) in MRAM.
7. A programmable resistive memory as recited in claim 1 , wherein programmable resistive element consists of at least one of a one-time-programmable (OTP) element.
8. A programmable resistive memory as recited in claim 7 , wherein OTP element consists at least one of a MOS device to trap charges or to be breakdown in gate oxide to determine the program state.
9. A programmable resistive memory as recited in claim 7 , wherein OTP element comprises a metal oxide, such as Indium Tin Oxide (ITO), Zinc Oxide (ZnO), Indium Zinc Oxide (IZO), or Indium Gallium Zinc Oxide (IGZO).
10. A programmable resistive memory as recited in claim 7 , wherein OTP element comprises an organic semiconductor, such as polymer of thiophene molecules or PMMA (polymethyl-methacrylate).
11. A programmable resistive memory as recited in claim 7 , wherein OTP element has a substantially rectangular shape or in serpentine structure.
12. A programmable resistive memory as recited in claim 7 , wherein OTP element has an OTP body between two nearest contacts in two ends, and has a length-to-width ratio of between 10 to 80 in the OTP body.
13. A programmable resistive memory as recited in claim 7 , wherein the OTP element has at least one bend in the body of OTP element.
14. A programmable resistive memory as recited in claim 7 , wherein the OTP element has more contacts at one end than at another end.
15. An electronics system, comprising:
a processor; and
a programmable resistive memory operatively connected to the processor, the programmable resistive memory including a plurality of programmable resistive cells, at least one of the cells comprising:
a programmable resistive element (PRE) having one end coupled to a first supply voltage line;
a selector having at least a first active region and a second active region, where the first active region having a first type of dopant and a second active region having a first or a second type of dopant, the first active region providing a first terminal of the selector, the second active region providing a second terminal of the selector, both the first and second active regions built on a non-single-crystal-silicon semiconductor film on an insulator substrate, the first active region coupled to the PRE and the second active region coupled to a second supply voltage line; and
a gate fabricated on the layer of non-single-crystal-silicon semiconductor with a sandwich of dielectric in between, the gate coupled to a third supply voltage line to control the conductivity between the first and the second active region; and
wherein the PRE is configured to be programmable by applying voltages to the first, second, and/or the third supply voltage lines to thereby change its logic state.
16. A programmable resistive memory as recited in claim 15 , wherein the substrate substantially consists of a glass, plastic, paper, metal, cellular or any kinds of flexible film.
17. A programmable resistive memory as recited in claim 15 , wherein the non-single-crystal-silicon semiconductor film substantially consists of at least one of amorphous silicon, polycrystalline silicon (polysilicon), silicon-germanium, organic or metal oxide semiconductor.
18. A programmable resistive memory as recited in claim 15 , wherein the programmable resistive element includes an OTP element that has at least one MOS device to trap charges or to be breakdown in gate oxide to determine the program state.
19. A programmable resistive memory as recited in claim 15 , wherein the programmable resistive element includes at least one electrode, the electrode including Indium Tin Oxide (ITO), Zinc Oxide (ZnO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), molecules of thiophene, or PMMA.
20. A method for operating a programmable resistive memory on a non-single-crystal-silicon semiconductor, the method comprises:
providing a plurality of programmable resistive cells, at least one of the programmable resistive cells includes at least (i) a programmable resistive element having one end coupled to a first supply voltage line; and (ii) a selector having at least one first active region and a second active region, where the first active region having a first type of dopant and the second region having a first or a second type of dopant, both the first and second active regions being fabricated on an insulator substrate, the first active region coupled to the OTP element, and the second active region coupled to a second supply voltage line, (iii) a gate fabricated on the non-crystalline semiconductor with a sandwich of dielectric in between, the gate coupled to a third supply voltage to control the conductivity between the first and the second active regions; and
programming a logic state into at least one of the programmable resistive cells by applying voltages to the first, the second, and/or the third voltage lines.