Low power chip-to-chip bidirectional communications
Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.
1. A method comprising:
receiving, at a receiver, symbols of a codeword, the symbols received via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix;
generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC receiving a corresponding subset of the symbols of the codeword and having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, each comparator output indicative of the weight applied to the corresponding sub-channel vector;
outputting a set of forward-channel output bits formed based on the plurality of comparator outputs; and
generating a sequence of bits of a secondary data link carried by common-mode sub-channel constituent codewords using a common-mode MIC receiving all symbols of the codeword and having input coefficients associated with the common-mode sub-channel vector.
2. The method of claim 1 , further comprising obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode sub-channel constituent codewords over the wires of the multi-wire bus, each common-mode sub-channel constituent codeword transmitted by modulating weights of the common-mode sub-channel vector according to a corresponding bit in the sequence of reverse-channel bits.
3. The method of claim 2 , wherein the sequence of reverse-channel bits is transmitted in a time interval when the sequence of bits of the secondary data link is not being generated.
4. The method of claim 1 , wherein the sequence of bits of the secondary data link are generated at a rate that is less than a rate of the forward-channel output bits.
5. The method of claim 4 , wherein the rate of the sequence of bits of the secondary data link is 256 times slower than the rate of the forward-channel output bits.
6. The method of claim 1 , further comprising de-serializing the sequence of bits of the secondary data link.
7. The method of claim 1 , wherein the sequence of bits of the secondary data link are associated with messages selected from the group consisting of: command messages, error information messages, and management information messages.
8. The method of claim 1 , wherein the orthogonal matrix is represented by M:
M
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9. The method of claim 1 , wherein the common-mode sub-channel constituent codewords are associated with a modulation of a baseline voltage of the wires of the multi-wire bus.
10. The method of claim 1 , wherein the common-mode sub-channel constituent codewords are generated by a transmitter sourcing and sinking current into the wires of the multi-wire bus.
11. An apparatus comprising:
a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant configured to:
receive symbols of a codeword, the symbols received via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix; and
generate a plurality of comparator outputs, each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, each comparator output indicative of the weight applied to the corresponding sub-channel vector;
a common-mode MIC configured to receive all symbols of the codeword, and to responsively generate a sequence of common-mode comparator outputs based on a set of input coefficients associated with the common-mode sub-channel vector; and
a plurality of samplers configured to output a set of forward-channel output bits formed by slicing the plurality of comparator outputs, and to output a sequence of bits of a secondary data link by slicing the sequence of common-mode comparator outputs.
12. The apparatus of claim 11 , further comprising a line driver configured to obtain a sequence of reverse-channel bits, and to transmit the sequence of reverse-channel bits by sequentially transmitting common-mode constituent codewords over the wires of the multi-wire bus, each common-mode constituent codeword transmitted by modulating weights of the common-mode sub-channel vector according to a corresponding bit in the sequence of reverse-channel bits.
13. The apparatus of claim 12 , wherein the line driver is configured to selectively transmit the reverse-channel bits in a time interval when the sequence of bits of the secondary data link are not being generated.
14. The apparatus of claim 11 , wherein the sequence of bits of the secondary data link are generated at a rate that is less than a rate of the forward-channel output bits.
15. The apparatus of claim 14 , wherein the rate of the sequence of bits of the secondary data link is 256 times slower than the rate of the forward-channel output bits.
16. The apparatus of claim 11 , further comprising a de-serializer configured to generate a multi-bit message from the sequence of bits of the secondary data link.
17. The apparatus of claim 16 , wherein the multi-bit message is selected from the group consisting of: command messages, error information message, and management information message.
18. The apparatus of claim 11 , wherein the sequence of bits of the secondary data link are conveyed by a transmitter configured to modulate a baseline voltage of the wires of the multi-wire bus to generate common-mode sub-channel constituent codewords.
19. The apparatus of claim 18 , wherein the transmitter comprises a plurality of switched-current sources configured to sink and supply current to the wires of the multi-wire bus to transmit the common-mode sub-channel constituent codewords.
20. The apparatus of claim 11 , wherein the orthogonal matrix is represented by M:
M
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