High voltage semiconductor device and manufacturing method of high voltage semiconductor device
A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.
1. A semiconductor device, comprising:
a deep well region located on a substrate;
a drift region located in the deep well region, wherein there is a P-N junction located between the drift region and the deep well region;
a first body region and a second body region formed to enclose the drift region, wherein each of the first body region and the second body region has a depth deeper than a depth of the drift region;
a first gate electrode that overlaps with the first body region and the drift region;
a second gate electrode that overlaps with the second body region and the drift region;
a first source region and a second source region located in the first and second body regions, respectively;
a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode;
a silicide layer located on the substrate;
a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer is insulative and extends over a top surface of the first gate electrode; and
a first field plate contact plug in contact with the first non-silicide layer.
2. The semiconductor device of claim 1 , further comprising:
a first source contact plug in contact with the first source region;
a drain contact plug in contact with the drain region; and
a first gate contact plug in contact with the first gate electrode,
wherein the first field plate contact plug is electrically connected with either one or both of the first gate contact plug and the first source contact plug.
3. The semiconductor device of claim 1 , further comprising:
a first body contact region located in the first body region and located adjacent to the first source region;
a second body contact region located in the second body region and located adjacent to the second source region;
a second source contact plug in contact with the second source region;
a second gate contact plug in contact with the second gate electrode;
a first body contact plug in contact with the first body contact region;
a second body contact plug in contact with the second body contact region;
a second non-silicide layer located between the drain region and the second gate electrode, wherein the second non-silicide layer extends over a top surface of the second gate electrode; and
a second field plate contact plug in contact with the second non-silicide layer.
4. The semiconductor device of claim 1 , wherein the first non-silicide layer comprises:
a first insulating layer; and
a second insulating layer,
wherein the second insulating layer has a different etch selectivity from an etch selectivity of the first insulating layer.
5. The semiconductor device of claim 1 , further comprising:
a first buried layer located on the substrate; and
a second buried layer located between the drift region and the first buried layer, wherein the second buried layer is in direct contact with the drift region and the second buried layer has a length smaller than a length of the first buried layer.
6. The semiconductor device of claim 1 , further comprising:
a borderless contact etch stopping layer located on the first non-silicide layer and the silicide layer;
an interlayer insulating layer located on the borderless contact etch stopping layer; and
a metal layer located on the interlayer insulating layer.
7. The semiconductor device of claim 1 , further comprising a ring-type body region that is formed by connecting the first body region to the second body region.
8. A semiconductor device, comprising:
a deep well region located on a substrate;
a drift region that overlaps with the deep well region, wherein there is a P-N junction located between the drift region and the deep well region;
a ring-type body region formed to enclose the drift region, wherein a first end of the ring-type body region extends outside the drift region;
a first gate electrode and a second gate electrode located on the drift region and on the ring-type body region, wherein a second end of the ring-type body region overlaps with the first gate electrode and the second gate electrode;
a first source region and a second source region located in the ring-type body region;
a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode;
a silicide layer located on the substrate;
a first non-silicide layer located on the drift region and overlapping with the first gate electrode, the first non-silicide layer being insulative; and
a first field plate contact plug located in contact with the first non-silicide layer.
9. The semiconductor device of claim 8 , further comprising:
a first source contact plug in contact with the first source region;
a drain contact plug in contact with the drain region; and
a first gate contact plug located on the first gate electrode,
wherein the first field plate contact plug is electrically connected with either one or both of the first gate contact plug and the first source contact plug.
10. The semiconductor device of claim 9 , further comprising:
a first body contact region located in the ring-type body region and located adjacent to the first source region;
a second body contact region located in the ring-type body region and located adjacent to the second source region;
a second source contact plug in contact with the second source region;
a second gate contact plug in contact with the second gate electrode;
a first body contact plug in contact with the first body contact region;
a second body contact plug in contact with the second body contact region;
a second non-silicide layer located between the drain region and the second gate electrode, wherein the second non-silicide layer extends over a top surface of the second gate electrode; and
a second field plate contact plug in contact with the second non-silicide layer.
11. The semiconductor device of claim 10 ,
wherein the first non-silicide layer is spaced apart from the ring-type body region, the first gate contact plug, and the drain contact plug, and
wherein the second non-silicide layer is spaced apart from the ring-type body region, the second gate contact plug, and the drain contact plug.
12. The semiconductor device of claim 8 , wherein the first field plate has a length smaller than a length of the first gate electrode in a same direction.
13. The semiconductor device of claim 10 , wherein the semiconductor device has a symmetric structure with respect to the drain contact plug.
14. The semiconductor device of claim 10 , wherein the ring-type body region has a depth deeper than a depth of the drift region and comprises a first body region and a second body region.
15. A semiconductor device, comprising:
a deep well region located on a substrate;
a drift region located in the deep well region;
a first body region and a second body region formed to enclose the drift region;
a first gate electrode that overlaps with the first body region and the drift region;
a second gate electrode that overlaps with the second body region and the drift region;
a first source region and a second source region located in the first and second body regions, respectively;
a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode;
a silicide layer located on the substrate;
a first non-silicide layer located between the drain region and the first gate electrode, the first non-silicide layer being insulative; and
a first field plate contact plug in contact with the first non-silicide layer.
16. The semiconductor device of claim 15 , wherein there is a P-N junction located between the drift region and the deep well region.
17. The semiconductor device of claim 15 , wherein each of the first body region and the second body region has a depth deeper than a depth of the drift region.
18. The semiconductor device of claim 15 , wherein the first non-silicide layer extends over a top surface of the first gate electrode.