Using a liner layer to enlarge process window for a contact via
In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.
1. An integrated chip comprising:
a substrate;
a source/drain region arranged along the substrate;
a first contact layer comprising a metal overlying the substrate;
a gate electrode overlying the substrate and laterally spaced from the first contact layer;
a first spacer structure surrounding outermost sidewalls of the first contact layer and separating the gate electrode from the first contact layer;
a first hard mask structure comprising a dielectric arranged directly over the first contact layer and between portions of the first spacer structure;
a first contact via extending through the first hard mask structure and contacting the first contact layer; and
a first liner layer arranged directly between a sidewall of the first hard mask structure and a sidewall of the first spacer structure.
2. The integrated chip of claim 1 , wherein the first liner layer separates the first hard mask structure from the first contact layer.
3. The integrated chip of claim 1 , wherein the first spacer structure has a first thickness measured in a lateral direction from a first inner sidewall to a first outer sidewall that is a minimum thickness of the first spacer structure, wherein the first spacer structure has a second thickness, different from the first thickness, measured in the lateral direction from the first inner sidewall to the first outer sidewall measured in the lateral direction that is a maximum thickness of the first spacer structure, and wherein the first thickness and the second thickness are measured at heights that are above a top surface of the first contact layer.
4. The integrated chip of claim 1 , wherein the first liner layer is arranged directly between the first contact layer and the first contact via.
5. The integrated chip of claim 1 , wherein the first liner layer is arranged over first and second topmost surfaces of the first spacer structure.
6. The integrated chip of claim 1 , further comprising:
a second contact layer overlying the substrate, wherein the gate electrode is between the first and second contact layers;
a second spacer structure surrounding outermost sidewalls of the second contact layer and separating the gate electrode from the second contact layer;
a second hard mask structure arranged over the second contact layer and between the second spacer structure;
a second contact via extending through the second hard mask structure and contacting the second contact layer; and
a second liner layer arranged directly between the second hard mask structure and the second spacer structure.
7. The integrated chip of claim 6 , wherein the first liner layer and the second liner layer do not contact one another.
8. An integrated chip comprising:
a substrate;
a source/drain region arranged along the substrate;
a contact layer comprising a metal overlying the substrate;
a gate electrode overlying the substrate and laterally spaced from the contact layer;
a spacer structure surrounding outermost sidewalls of the contact layer and separating the gate electrode from the contact layer;
a hard mask structure arranged directly over the contact layer and directly between portions of the spacer structure;
a contact via extending through the hard mask structure and contacting the contact layer; and
a liner layer comprising a dielectric arranged directly between the hard mask structure and the contact layer.
9. The integrated chip of claim 8 , wherein the liner layer comprises a different material than the hard mask structure and the spacer structure.
10. The integrated chip of claim 8 , wherein the liner layer directly contacts a topmost surface of the spacer structure.
11. The integrated chip of claim 8 , wherein the liner layer has a topmost surface that is below a topmost surface of the spacer structure.
12. The integrated chip of claim 8 ,
wherein the hard mask structure has a topmost surface at a first height measured in a vertical direction from a topmost surface of the contact layer;
wherein the liner layer has a topmost surface a second height measured in the vertical direction from the topmost surface of the contact layer; and
wherein a ratio of the second height to the first height is between about 10 percent and about 100 percent.
13. The integrated chip of claim 8 , the contact via does not directly overlie the liner layer.
14. An integrated chip comprising:
a substrate;
a source/drain region arranged along the substrate;
a contact layer comprising a metal arranged over the substrate;
a gate electrode arranged over the substrate and laterally beside the contact layer;
a spacer structure arranged over the substrate, directly between the contact layer and the gate electrode, and along outer sidewalls of the contact layer;
a liner layer comprising a dielectric arranged on inner sidewalls of the spacer structure and directly over a top surface of the contact layer;
a hard mask structure arranged over the liner layer, the spacer structure, and the contact layer; and
a contact via extending through the hard mask structure and the liner layer to contact the contact layer, wherein the liner layer comprises a different material than the hard mask structure and the spacer structure.
15. The integrated chip of claim 14 , wherein an upper portion of the spacer structure has a thickness measured in the lateral direction that increases from a topmost surface of the spacer structure toward a bottommost surface of the spacer structure, and wherein the upper portion is arranged completely above a topmost surface of the gate electrode.
16. The integrated chip of claim 14 , wherein the contact via directly contacts the spacer structure.
17. The integrated chip of claim 14 , wherein the liner layer extends over upper surfaces of the spacer structure.
18. The integrated chip of claim 14 , wherein a maximum thickness of the spacer structure that is measured in the lateral direction is arranged above the gate electrode.
19. The integrated chip of claim 14 , wherein the liner layer comprises a dielectric material that has a higher dielectric constant than a material of the hard mask structure.
20. The integrated chip of claim 14 , wherein the liner layer comprises a dielectric material that has a higher dielectric constant than a material of the spacer structure.