Integrated circuit device and method of manufacturing the same

1. An integrated circuit device comprising:

a conductive line formed on a substrate, the conductive line comprising a metal layer and extending in a first horizontal direction with respect to an upper surface of the substrate;

an insulation capping structure disposed on an upper surface of the conductive line,

wherein the insulation capping structure comprises:

a first insulation capping pattern having a first density, the first insulation capping pattern being adjacent to the metal layer; and

a second insulation capping pattern vertically spaced apart from the metal layer with the first insulation capping pattern therebetween, the second insulation capping pattern having a second density that is greater than the first density; and

a contact structure including a vertical portion extending in a vertical direction with respect to the upper surface of the substrate and being spaced apart from side walls of the conductive line and side walls of the insulation capping structure in a second horizontal direction with respect to the upper surface of the substrate, the second horizontal direction being perpendicular to the first horizontal direction.

2. The integrated circuit device of claim 1 , wherein

the first insulation capping pattern and the second insulation capping pattern contact each other, and

a width of the first insulation capping pattern in a second horizontal direction with respect to the upper surface of the substrate is equal to a width of the second insulation capping pattern in the second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction.

3. The integrated circuit device of claim 1 ,

wherein the first insulation capping pattern is in contact with an entire upper surface of the metal layer,

wherein the metal layer comprises a first region doped with nitrogen atoms, the first region extending from an interface between the metal layer and the first insulation capping pattern toward the substrate and having a first thickness less than a thickness of the metal layer, and

wherein the nitrogen atoms are in a diffused state in the first region without being chemically bonded with atomic elements of the metal layer.

4. The integrated circuit device of claim 3 , wherein

the first thickness of the first region of the metal layer is between 5 Å to 40 Å.

5. The integrated circuit device of claim 1 , wherein

a bottom surface of the first insulation capping pattern is in contact with an upper surface of the metal layer, and

a bottom surface of the second insulation capping pattern is in contact with an upper surface of the first insulation capping pattern.

6. The integrated circuit device of claim 1 , wherein

the first insulation capping pattern and the second insulation capping pattern each comprise a silicon nitride layer.

7. The integrated circuit device of claim 1 , wherein

the first insulation capping pattern comprises a silicon carbonitride layer and the second insulation capping pattern comprises a silicon nitride layer.

8. The integrated circuit device of claim 1 , wherein

the conductive line comprises a lower conductive pattern, an intermediate conductive pattern, and an upper conductive pattern that are sequentially stacked on the substrate, and

the lower conductive pattern comprises doped polysilicon, the intermediate conductive pattern comprises TiN, TiSiN, or a combination thereof, and the upper conductive pattern comprises tungsten (W).

9. An integrated circuit device comprising:

a pair of bit lines extending on a substrate in parallel to each other in a first horizontal direction with respect to an upper surface of the substrate, the pair of bit lines being adjacent to each other in a second horizontal direction with respect to the upper surface of the substrate;

a pair of insulation capping structures contacting the pair of bit lines, respectively; and

a contact structure including a vertical portion extending in a vertical direction from a region between the pair of bit lines to a region between the pair of insulation capping structures, wherein the vertical portion is spaced apart from each of the pair of bit lines and each of the pair of insulation structures,

wherein the pair of bit lines each comprise a metal layer, and

each of the pair of insulation capping structures comprises:

a first insulation capping pattern on the metal layer, the first insulation capping pattern having a first density; and

a second insulation capping pattern spaced apart from the metal layer with the first insulation capping pattern therebetween, the second insulation capping pattern having a second density that is greater than the first density.

10. The integrated circuit device of claim 9 , wherein,

in at least one of the pair of insulation capping structures, a width of the first insulation capping pattern in the second horizontal direction is equal to a width of the second insulation capping pattern in the second horizontal direction.

11. The integrated circuit device of claim 9 , wherein

the first insulation capping pattern is in contact with the metal layer, and

the metal layer comprises a tungsten (W) layer that is in contact with the first insulation capping pattern, the tungsten (W) layer comprising tungsten (W) atoms and nitrogen (N) atoms, the nitrogen (N) atoms being distributed among the tungsten (W) atoms of a partial area, in contact with the first insulation capping pattern, of the tungsten (W) layer without any chemical reaction with the tungsten (W) atoms, and tungsten nitride particles distributed in the tungsten (W) layer.

12. The integrated circuit device of claim 9 , wherein,

in at least one of the pair of insulation capping structures, a bottom surface of the first insulation capping pattern is in contact with an upper surface of the metal layer and

a bottom surface of the second insulation capping pattern is in contact with an upper surface of the first insulation capping pattern.

13. The integrated circuit device of claim 9 , wherein,

in the pair of insulation capping structures, each of the first insulation capping pattern and the second insulation capping pattern comprises a silicon nitride layer.

14. The integrated circuit device of claim 9 , wherein,

in the pair of insulation capping structures, the first insulation capping pattern comprises a silicon carbonitride layer, and

the second insulation capping pattern comprises a silicon nitride layer.

15. The integrated circuit device of claim 9 , further comprising

a contact structure between the pair of insulation capping structures.

16. An integrated circuit device comprising:

a substrate comprising a cell array area and a peripheral circuit area;

a bit line on the substrate in the cell array area, the bit line comprising a first metal layer;

a first insulation capping structure covering the bit line in the cell array area;

a gate electrode on the substrate in the peripheral circuit area, the gate electrode comprising a second metal layer; and

a second insulation capping structure covering the gate electrode in the peripheral circuit area,

wherein each of the first insulation capping structure and the second insulation capping structure comprises:

a first insulation capping pattern having a first density; and

a second insulation capping pattern spaced apart from the substrate with the first insulation capping pattern therebetween, the second insulation capping pattern having a second density that is greater than the first density, and

the first metal layer and the second metal layer are in contact with the first insulation capping pattern included in the first insulation capping structure and the first insulation capping pattern included in the second insulation capping structure, respectively, and

the first metal layer comprises a first region doped with nitrogen (N) atoms, the first region extending from an interface between the first metal layer and the first insulation capping pattern in the first insulation capping structure toward the substrate and having a first thickness less than a thickness of the first metal layer.

17. The integrated circuit device of claim 16 , wherein

the first region of the first metal layer has a thickness between 5 Å to 40 Å.

18. The integrated circuit device of claim 16 , wherein

the first metal layer comprises a tungsten (W) layer that is in contact with the first insulation capping pattern in the first insulation capping structure,

the tungsten (W) layer comprising nitrogen (N) atoms and tungsten (W) atoms, the nitrogen (N) atoms being distributed among the tungsten (W) atoms of a partial area, in contact with the first insulation capping pattern, of the W layer without any chemical reaction with the tungsten (W) atoms, and tungsten nitride particles distributed in the W layer.

19. The integrated circuit device of claim 16 , wherein

a bottom surface of the second insulation capping pattern is in contact with an upper surface of the first insulation capping pattern,

the first insulation capping pattern comprises a silicon nitride layer, a silicon carbonitride layer, or a combination thereof, and

the second insulation capping pattern comprises a silicon nitride layer.

20. The integrated circuit device of claim 1 ,

wherein an insulation capping structure is disposed on the upper surface of the conductive line without covering side walls of the conductive line.