IP Library Granted Patent US 10,840,216
Granted Patent B2
US 10,840,216 · App. 16/810,520 · Granted Nov 17, 2020

Systems and methods for powering an integrated circuit having multiple interconnected die

Inventor: Jean-Philippe Fricker (Los Altos, CA)
Assignee: Cerebras Systems Inc.
H01L25/0655H01L23/32H01L23/367H01L23/473H01L23/49811H01L23/49827H01L24/48H01L2224/48137
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Quick Facts
Patent No.
US 10,840,216
App. No.
16/810,520
Granted
Nov 17, 2020
Kind
B2
Abstract

The power on wafer assembly can include: a compliant connector, an integrated circuit, a printed circuit board (PCB), a power component, and a set of compliant connectors. The power on wafer assembly can optionally include: a compression element, a cooling system, a set of mechanical clamping components, and a power source. However, the power on wafer assembly can additionally or alternately include any other suitable components.

Claims (25)

1. An assembly comprising:

a printed circuit board (PCB) defining a first surface of the PCB;

a semiconductor, defining a second surface of the semiconductor, comprising:

a substrate; and

a first die and a second die formed within the substrate;

a first and second power converter arranged between the first surface of the PCB and the second surface of the semiconductor, the first and second power converters electrically connected to the first and second die, respectively;

a compliant connector electrically connecting the PCB and the first power converter;

a first cold plate, arranged between the first power converter and the PCB, that is thermally connected to the first power converter;

a fluid reservoir; and

a fluid manifold extending through a thickness of the PCB and connecting the first cold plate to the reservoir,

wherein the second power converter is electrically coupled to the PCB.

2. The assembly of claim 1 , wherein the semiconductor further comprises:

a circuit layer formed at each of the first and second die; and

a plurality of inter-die connections communicatively connecting the first and second die.

3. The assembly of claim 1 , further comprising a compression element arranged between the PCB and the first power converter.

4. The assembly of claim 3 , wherein the compression element comprises the compliant connector.

5. The assembly of claim 3 , further comprising a plurality of clamping components mechanically coupling the PCB to the semiconductor and preloading the compression element.

6. The assembly of claim 1 , further comprising:

a second cold plate arranged proximate a third surface of the semiconductor opposite the second surface of the semiconductor;

wherein the fluid manifold fluidly connects the first cold plate and the second cold plate.

7. The assembly of claim 1 , wherein the semiconductor comprises a wafer-scale processor.

8. The assembly of claim 1 , wherein the power converter comprises a voltage regulator, a current transformer, and a driver.

9. The assembly of claim 1 , further comprising:

a power source opposing the first power converter across a thickness of the PCB; and

a via extending through a thickness of the PCB, the via electrically connecting the power source to the compliant connector.

Assignments (2)
SECURITY INTEREST Recorded Jun 18, 2026
From: CEREBRAS SYSTEMS INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 075845/0844 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2020
From: FRICKER, JEAN-PHILIPPE
To: CEREBRAS SYSTEMS INC.
Reel/Frame 052101/0875 →
Continuity (2)
Provisional Application 62813889 · Mar 5, 2019
Related Publication 20200286858A1 · Sep 10, 2020