Techniques to transfer data among hardware devices
Apparatuses, systems, and techniques to route data transfers between hardware devices. In at least one embodiment, a path over which to transfer data from a first hardware component of a computer system to a second hardware component of a computer system is determined based, at least in part, on one or more characteristics of different paths usable to transfer the data.
1. A processor comprising:
one or more circuits to determine a path over which to transfer data from a first hardware component of a computer system to a second hardware component of the computer system based, at least in part, on a device tree and one or more characteristics of different paths usable to transfer the data.
2. The processor of claim 1 , wherein one or more of the first hardware component and the second hardware component is a graphics processing unit (GPU).
3. The processor of claim 1 , wherein the device tree is a representation of a hardware topology that includes the first hardware component and the second hardware component.
4. The processor of claim 3 , wherein the device tree is a device hierarchy tree, and the one or more circuits are further to generate the device hierarchy tree based, at least in part, on peripheral component interconnect express (PCIe) bus device function (BDF) information.
5. The processor of claim 3 , wherein the first hardware component is controlled by a first operating system (OS) instance, the second hardware component is controlled by a second OS instance, and the first hardware component and the second hardware component are connected on an inter-node path that includes at least one of a memory fabric or a network fabric.
6. The processor of claim 1 , wherein the one or more circuits are further to determine a set of available block devices, and to determine the path based, at least in part, on the set of available block devices.
7. The processor of claim 1 , wherein the path includes a buffer managed by an intermediate device.
8. The processor of claim 7 , wherein the one or more circuits are further to determine that the buffer allows direct memory access (DMA) and has a predetermined amount of space available.
9. The processor of claim 1 , wherein the one or more circuits are further to determine a set of available block devices, and to determine the path based, at least in part, on a set of available links.
10. The processor of claim 1 , wherein the one or more circuits are further to determine a plurality of values corresponding to a plurality of dynamic component conditions, and to determine the path based, at least in part, on the plurality of values.
11. A non-transitory machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least:
determine a path over which to transfer data from a first hardware component of a computer system to a second hardware component of the computer system based, at least in part, on one or more characteristics of different paths usable to transfer the data, wherein one or more of the first hardware component and the second hardware component is a graphics processing unit GPU).
12. The non-transitory machine-readable medium of claim 11 , wherein the instructions, which if performed by the one or more processors, further cause the one or more processors to determine the path based, at least in part, on a representation of a hardware topology that includes the first hardware component and the second hardware component.
13. The non-transitory machine-readable medium of claim 12 , wherein the representation of the hardware topology is a device hierarchy tree, and the instructions, which if performed by the one or more processors, further cause the one or more processors to generate the device hierarchy tree based, at least in part, on peripheral component interconnect express (PCIe) bus device function (BDF) information.
14. The non-transitory machine-readable medium of claim 11 , wherein the instructions, which if performed by the one or more processors, further cause the one or more processors to determine a set of available block devices, and to determine the path based, at least in part, on the set of available block devices.
15. The non-transitory machine-readable medium of claim 11 , wherein the path includes a buffer managed by an intermediate device.
16. The non-transitory machine-readable medium of claim 15 , wherein the instructions, which if performed by the one or more processors, further cause the one or more processors to determine that the buffer allows direct memory access (DMA) and has a predetermined amount of space available.
17. The non-transitory machine-readable medium of claim 11 , wherein the instructions, which if performed by the one or more processors, further cause the one or more processors to determine a plurality of values corresponding to a plurality of dynamic component conditions, and to determine the path based, at least in part, on the plurality of values.
18. A method comprising:
determining a path over which to transfer data from a first hardware component of a computer system to a second hardware component of the computer system based, at least in part, on a device tree and one or more characteristics of different paths usable to transfer the data.
19. The method of claim 18 , further comprising transferring a set of data from the first hardware component to the second hardware component via the path.
20. The method of claim 18 , wherein one or more of the first hardware component and the second hardware component is a graphics processing unit (GPU).
21. The method of claim 18 , wherein the device tree is a representation of a hardware topology that includes the first hardware component and the second hardware component.
22. The method of claim 18 , further comprising: determining a set of available block devices, wherein determining the path is based, at least in part, on the set of available block devices.
23. The method of claim 18 , wherein the path includes a buffer managed by an intermediate device.
24. The method of claim 23 , further comprising: determining that the buffer allows direct memory access (DMA) and has a predetermined amount of space available.
25. The method of claim 18 , further comprising: determining a plurality of values corresponding to a plurality of dynamic component conditions, wherein determining the path is based, at least in part, on the plurality of values.
26. A system comprising:
one or more processors to determine a path over which to transfer data from a first hardware component of a computer system to a second hardware component of the computer system based, at least in part, on one or more characteristics of different paths usable to transfer the data; and
one or more memories to store a set of data that represents the path, wherein one or more of the first hardware component and the second hardware component is a graphics processing unit (GPU).
27. The system of claim 26 , wherein the one or more processors are to determine the path based, at least in part, on a representation of a hardware topology that includes the first hardware component and the second hardware component.
28. The system of claim 27 , wherein the representation of the hardware topology is a device hierarchy tree, ant the one or more processors are further to generate the device hierarchy tree based, at least in part, on peripheral component interconnect express (PCIe) bus device function (BDF) information.
29. The system of claim 26 , wherein the one or more processors are further to determine a set of available block devices, and to determine the path based, at least in part, on the set of available block devices.
30. The system of claim 26 , wherein the path includes a buffer managed by an intermediate device.
31. The system of claim 30 , wherein the one or more processors are further to determine that the buffer allows direct memory access (DMA) and has a predetermined amount of space available.
32. The system of claim 26 , wherein the one or more processors are further to determine a plurality of values corresponding to a plurality of dynamic component conditions, and to determine the path based, at least in part, on the plurality of values.