Hardware assisted page migration in a multi-dielet processing system
A hardware mechanism at each dielet of a multi-dielet processing system is aware of engine page-table binds at all the dielets, thereby providing accurate traffic notifications to software (e.g., a unified virtual memory driver) for on-demand page-migration between system memory and GPU memory. The mechanism broadcasts binding information to access counters on each dielet so the access counters are able to correlate engines requesting memory access with bound virtual memory pages and generate corresponding informative notifications. A flexible multi-dielet counter clear capability enables software to clear access counters.
1 . A method comprising:
communicating a memory binding to a first circuit on a first dielet and to a second circuit on at least one further dielet;
then receiving a memory access request; and
conditionally generating a page migration notification on the first dielet or the at least one further dielet based on associating the received memory access request with the previously communicated memory binding, when the received memory access request causes the first circuit and/or the second circuit to indicate memory access traffic above a threshold to a page associated with the communicated memory binding.
2 . The method of claim 1 wherein the generating is performed by only one of the first circuit and the second circuit.
3 . The method of claim 2 further including receiving a memory binding request and broadcasting a responsive memory binding acknowledgement to each of the first circuit on the first dielet and the second circuit on the at least one further dielet.
4 . The method of claim 1 further comprising:
tracking memory accesses and selectively generating notifications for use in memory page migration;
wherein the first dielet and the at least one further dielet are disposed on a first multi-chip module, and the tracking tracks memory accesses originating from an engine disposed on another multi-chip module.
5 . The method of claim 1 wherein generating generates the page migration notification to indicate there is sufficient traffic to migrate the page from a remote memory to a local memory.
6 . The method of claim 1 further including:
receiving a remote memory update with same virtual engine identifier (VEID) based on an engine with that VEID generating the memory access request,
looking up the corresponding bind information, and
using the corresponding bind information to trigger the page migration notification that a virtual memory page associated with a corresponding Instance-Block-Pointer (IBP) is a candidate for page migration.
7 . The method of claim 6 wherein generating triggers the page migration notification upon an access counter being incremented enough times.
8 . The method of claim 1 wherein the first circuit and the second circuit each monitor and log memory accesses.
9 . The method of claim 1 wherein the first dielet and the at least one further dielet are part of a multi-chip module (MCM).
10 . The method of claim 1 further including presenting the first dielet and the at least one further dielet as a single monolithic integrated unitary high performance processing system.
11 . Apparatus comprising:
a first circuit disposed on a first dielet and configured to communicate a memory binding to the first dielet and to a further circuit disposed on a at least one further dielet;
a second circuit configured to receive a memory access request; and
a third circuit configured to generate a page migration notification on the first dielet or the at least one further dielet based on associating the received memory access request with a previously communicated memory binding;
the third circuit further configured to conditionally generate the page migration notification when the received memory access request causes one of the first circuit and the further circuit to indicate memory access traffic above a threshold to a page associated with the communicated memory binding.
12 . The apparatus of claim 11 wherein:
the third circuit generates the page migration notification on only one of the first dielet and the further dielet.
13 . The apparatus of claim 12 wherein the first circuit is further configured to broadcast a memory binding acknowledgement responsive to a memory binding request, to each of the first circuit on the first dielet and the further circuit on the at least one further dielet.
14 . The apparatus of claim 11 wherein the third circuit generates the page migration notification to indicate there is sufficient traffic to migrate the page from a remote memory to a local memory.
15 . The apparatus of claim 11 wherein the third circuit comprises an access counter circuit configured to:
receive a remote memory update with a same virtual engine identifier (VEID) based on an engine with that VEID generating the memory access request,
look up the corresponding bind information, and
use the corresponding bind information to trigger the page migration notification that a virtual memory page associated with a corresponding Instance-Block-Pointer (IBP) is a candidate for page migration.
16 . The apparatus of claim 15 wherein the access counter circuit triggers the page migration notification when it has been incremented enough times.
17 . The apparatus of claim 11 wherein the second circuit is configured to monitor and log memory accesses.
18 . The apparatus of claim 11 wherein the first dielet and the at least one further dielet are part of a multi-chip module (MCM).
19 . The apparatus of claim 11 wherein the first dielet and the at least one further dielet are presented as a single monolithic integrated unitary high performance processing system.