Packaged die stacks with stacked capacitors and methods of assembling same
A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.
1. A semiconductive apparatus, comprising:
a plurality of stacked dies on a package substrate;
a plurality of stacked capacitors associated with at least some of the dies in the plurality of stacked dies;
one or more through mold vias (TMVs) that communicate power between the plurality of stacked capacitors;
wherein the plurality of stacked capacitors are located on a periphery of the plurality of stacked dies.
2. The semiconductive apparatus of claim 1 , wherein there is at least one capacitor corresponding to each die in the plurality of stacked dies.
3. The semiconductive apparatus of claim 1 , wherein there are eight capacitors corresponding to each die in the plurality of stacked dies.
4. The semiconductive apparatus of claim 1 , wherein there are four capacitors on opposing sides of a die in the plurality of stacked dies.
5. The semiconductive apparatus of claim 1 , wherein stacked capacitors on two adjacent levels in the plurality of stacked capacitors share a common merged power rail.
6. The semiconductive apparatus of claim 1 , wherein the plurality of stacked dies and the plurality of stacked capacitors are encapsulated in one or more layers of a molding material.
7. The semiconductive apparatus of claim 1 , further including one or more through silicon vias (TSVs) that communicate power between levels to both the plurality of stacked dies and the plurality of stacked capacitors.