Stacked nanowire or nanosheet gate-all-around device and method for manufacturing the same
A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.
1. A stacked nanowire or nanosheet gate-all-around (GAA) device, comprising:
a silicon substrate;
stacked nanowires or nanosheets, located on the silicon substrate, wherein each of the stacked nanowires or nanosheets extends along a first direction, and the stacked nanowires or nanosheets comprises a plurality of nanowires or nanosheets that is stacked;
a gate stack, surrounding each of the stacked nanowires or nanosheets, wherein the gate stack extends along a second direction, first spacers are located on two sidewalls of the gate stack, and the sidewalls are in the first direction of the gate stack;
source-or-drain regions, located at two sides of the gate stack along the first direction; and
a channel region, comprising a portion of the stacked nanowires or nanosheets that is located between the first spacers;
wherein a notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, the notch structure comprises a first part and a second part, the first part is located on a middle of the notch structure, the second part is located on an upper side and a lower side of the first part in a direction perpendicular to the silicon substrate, and a width of the first part is less than a width of the second part; and
wherein the notch structure is oxidized from outside to inside, the first part is completely oxidized and is configured to provide an isolator for pinching off, the second part is partially oxidized, the isolator for pinching off is an oxide and is configured to isolate the stacked nanowires or nanosheets from the silicon substrate, and a height of the isolator for pinching off is greater than 3 nm.
2. The stacked nanowire or nanosheet GAA device according to claim 1 , wherein each of the stacked GAA nanowires or nanosheets is made of Si 1-y Ge y , and 0≤y≤1.
3. The stacked nanowire or nanosheet GAA device according to claim 1 , wherein:
a silicon-etched structure is located between the silicon substrate and the notch structure, or
a silicon-etched structure is located between the silicon substrate and the notch structure, and another silicon-etched structure is located between the gate stack and the notch structure.
4. The stacked nanowire or nanosheet GAA device according to claim 1 , wherein:
a strain-buffer structure is located between the silicon substrate and the notch structure, or
a strain-buffer structure is located between the silicon substrate and the notch structure, and another strain-buffer structure is located between the gate stack and the notch structure; and
wherein each of the strain-buffer structure and the another strain-buffer structure is made of Si 1-z Ge z , and 0≤z≤0.8.