Semiconductor device package comprising power module and passive elements
A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
1. A semiconductor device package, comprising:
a first substrate having a first surface and a second surface opposite to the first surface;
a computing unit adjacent to the first surface, the computing unit comprising a semiconductor die;
a power module adjacent to the second surface, the power module comprising a power element and a passive element;
a second substrate having a third surface and a fourth surface opposite to the third surface, the third surface facing the second surface of the first substrate; and
a via embedded in the second substrate and disposed between the passive element and the power element,
wherein each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive element is assembled between the semiconductor die and the power element.
2. The semiconductor device package of claim 1 ,
wherein the power element is adjacent to the fourth surface and the passive element is adjacent to the third surface.
3. The semiconductor device package of claim 1 , wherein the passive element is in contact with one of the second surface and the third surface.
4. The semiconductor device package of claim 3 , wherein the passive element comprises a first electrical terminal in contact with the third surface and a second electrical terminal in contact with the second surface.
5. The semiconductor device package of claim 3 , further comprising a cavity substrate between the first substrate and the second substrate, a cavity of the cavity substrate accommodating the passive element.
6. The semiconductor device package of claim 3 , wherein the passive element comprises inductors.
7. The semiconductor device package of claim 1 , wherein the passive element comprises capacitors between the first substrate and the second substrate.
8. The semiconductor device package of claim 1 , wherein the passive element comprises capacitors arranged vertically with respect to the semiconductor die.
9. The semiconductor device package of claim 1 , further comprising a first heat sink coupled to the computing unit.
10. The semiconductor device package of claim 9 , further comprising a second heat sink coupled to the power module.
11. A semiconductor device package, comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a computing unit adjacent to the first surface, the computing unit comprising a semiconductor die;
a power module adjacent to the second surface, the power module comprising a power element and an inductor stacked with the power element;
a passive element over the power module;
a printed circuit board (PCB) between the passive element and the power module; and
a via embedded in the PCB and disposed between the passive element and the power element,
wherein each of the semiconductor die, the power module, and the passive element is vertically arranged with respect to each other.
12. The semiconductor device package of claim 11 , wherein the PCB comprises a third surface and a fourth surface opposite to the third surface, the third surface facing the second surface of the substrate, and the power module is assembled on the fourth surface.
13. The semiconductor device package of claim 11 , wherein the power module is electrically connected to the computing unit through the inductor and the passive element.
14. The semiconductor device package of claim 11 , wherein the passive element is assembled between the semiconductor die and the power element.
15. A semiconductor device package, comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a computing unit adjacent to the first surface, the computing unit comprising a semiconductor die;
a printed circuit board (PCB) under the substrate, comprising a third surface and a fourth surface opposite to the third surface;
a power module adjacent to the fourth surface, the power module comprising:
a power element on the fourth surface; and
an inductor embedded in the PCB,
a passive element over the power module; and
a via embedded in the PCB and disposed between the passive element and the power element,
wherein each of the semiconductor die, the power module, the PCB, and the passive element is vertically arranged with respect to each other.
16. The semiconductor device package of claim 15 , wherein the passive element is a capacitor in contact with one of the second surface and the third surface.
17. The semiconductor device package of claim 15 , wherein the passive element comprises a first electrical terminal in contact with the third surface and a second electrical terminal in contact with the second surface.
18. The semiconductor device package of claim 15 , further comprising a conductive terminal connecting the second surface and the third surface, a height of the conductive terminal being greater than or substantially equal to a height of the passive element.
19. The semiconductor device package of claim 15 , wherein the power element is electrically connected to the semiconductor die through the inductor and the passive element.
20. The semiconductor device package of claim 1 , wherein the passive element is spaced apart from either the third surface of the second substrate or the second surface of the first substrate.
21. The semiconductor device package of claim 5 , wherein the second surface of the first substrate is exposed to the cavity of the cavity substrate.
22. The semiconductor device package of claim 5 , wherein the third surface of the second substrate is exposed to the cavity of the cavity substrate.
23. The semiconductor device package of claim 11 , wherein the power element is disposed between the inductor and the first substrate.
24. The semiconductor device package of claim 11 , further comprising a cavity substrate disposed between the first substrate and the power element, and the cavity substrate comprises a cavity accommodating the passive element and the inductor.
25. The semiconductor device package of claim 11 , further comprising a passive device laterally arranged with the inductor.
26. The semiconductor device package of claim 11 , wherein two terminals of the inductor are laterally arranged with respect to each other.