Semiconductor memory device and method of manufacturing the same

1. A method of manufacturing a semiconductor memory device, the method comprising:

forming a plurality of bit line structures extending in parallel with each other in a first horizontal direction on a substrate, and a plurality of insulating spacer structures covering opposite sidewalls of each of the plurality of bit line structures;

forming a preliminary buried contact material layer and a mold layer to respectively fill a lower portion of a space between a pair of insulating spacer structures of the plurality of insulating spacer structures and an upper portion of the space, the pair of insulating spacer structures facing each other across the space;

patterning the mold layer and the preliminary buried contact material layer into a plurality of mold patterns spaced apart from each other in a second horizontal direction different from the first horizontal direction and a plurality of buried contacts spaced apart from each other in the second horizontal direction, respectively;

forming a plurality of insulating fences among the plurality of mold patterns separated from each other and among the plurality of buried contacts separated from each other;

removing the plurality of mold patterns to expose the plurality of buried contacts; and

forming a plurality of landing pads on the plurality of exposed buried contacts, each of the plurality of landing pads connected to a corresponding one of the plurality of exposed buried contacts.

2. The method of claim 1 , further comprising,

after the forming of the preliminary buried contact material layer in the lower portion of the space and before forming the mold layer in the upper portion of the space, removing an upper portion of the plurality of insulating spacer structures above a top surface of the preliminary buried contact material layer.

3. The method of claim 2 , wherein

each of the plurality of bit line structures comprises a bit line and an insulating capping line covering the bit line, and

the removing of the upper portion of the plurality of insulating spacer structures exposes an upper portion of the insulating capping line of each of the plurality of bit line structures,

the method further comprising:

forming, after the removing the upper portion of the insulating spacer structures and before the forming of the mold layer, an expansion capping layer covering the exposed upper portion of the insulating capping line and protruding to the top surface of the preliminary buried contact material layer.

4. The method of claim 3 , wherein

each of the plurality of landing pads is formed to cover at least a portion of the expansion capping layer.

5. The method of claim 1 , wherein

the removing of the plurality of mold patterns forms a plurality of spaces, and

each of the plurality of landing pads is formed to fill a corresponding one of the plurality of spaces, and extends to a corresponding one of the plurality of bit line structures.

6. The method of claim 1 , wherein

each of the plurality of insulating fences is formed to have an upper portion with a first width and a lower portion with a second width different from the first width in the first horizontal direction,

the upper portion of each of the plurality of insulating fences is disposed between two adjacent landing pads of the plurality of landing pads, and

the lower portion of each of the plurality of insulating fences is disposed between two adjacent buried contact of the plurality of buried contacts.

7. The method of claim 1 , wherein

each of the plurality of insulating fences is formed to have an upper portion with a first width and a lower portion with a second width smaller than the first width in the first horizontal direction,

the upper portion of each of the plurality of insulating fences is disposed between two adjacent landing pads of the plurality of landing pads and

the lower portion of each of the plurality of insulating fences is disposed between two adjacent buried contacts of the plurality of buried contacts.

8. The method of claim 1 , wherein

each of the plurality of insulating fences is formed to have an upper portion with a first width and a lower portion with a second width greater than the first width in the first horizontal direction,

the upper portion of each of the plurality of insulating fences is disposed between two adjacent landing pads of the plurality of landing pads and

the lower portion of each of the plurality of insulating fences is disposed between two adjacent buried contacts of the plurality of buried contacts.

9. The method of claim 8 , wherein

each of the plurality of insulating fences is formed to include an air gap inside the lower portion thereof and the air gap is disposed between two adjacent buried contacts of the plurality of buried contacts.

10. The method of claim 1 , wherein

each of the plurality of insulating fences is formed to have an increasing width in a direction perpendicular to the substrate, and the increasing width is measured in the second horizontal direction.

11. A method of manufacturing a semiconductor memory device, the method comprising:

forming, on a substrate, a plurality of bit line structures, a plurality of first insulating spacer structures each of which covers a first sidewall of a corresponding one of the plurality of bit line structures, and a plurality of second insulating spacer structures each of which covers a second sidewall, opposite the first sidewall, of the corresponding one of the plurality of bit line structures;

forming a preliminary buried contact material layer and a mold layer on the substrate, wherein the preliminary buried contact material layer and the mold layer are formed in a first space between one of the plurality of first insulating spacer structures and one of the plurality of second insulating spacer structures adjacent thereto in a first horizontal direction, wherein the preliminary buried contact material layer fills a lower portion of the first space and the mold layer fills an upper portion thereof; and

patterning the mold layer and the preliminary buried contact material layer into a plurality of mold patterns spaced apart from each other in a second horizontal direction different from the first horizontal direction and a plurality of buried contacts spaced apart from each other in the second horizontal direction;

forming a plurality of insulating fences among the plurality of buried contacts and the plurality of mold patterns, a first insulating fence of the plurality of insulating fences having a lower portion and an upper portion, the lower portion of the first insulating fence being disposed between a pair of buried contacts, spaced apart from each other in the second horizontal direction, among a plurality of buried contacts and having a first width in the second horizontal direction, and the upper portion of the first insulating fence being disposed between a pair of mold patterns, spaced apart from each other in the second horizontal direction, among a plurality of mold patterns and having a second width in the second horizontal direction different from the first width.

12. The method of claim 11 , further comprising:

removing the plurality of mold patterns to expose the plurality of buried contacts; and

forming a plurality of landing pads to fill a second space formed by removing the plurality of mold patterns.

13. The method of claim 11 , wherein

the second width of the upper portion of the first insulating fence is greater than the first width of the lower portion of the first insulating fence.

14. The method of claim 11 , further comprising:

forming an air gap in the first insulating fence,

wherein the second width of the upper portion of the first insulating fence is less than the first width of the lower portion of the first insulating fence.

15. A method of manufacturing a semiconductor memory device, the method comprising:

preparing a substrate having a plurality of active regions defined by an element separation layer;

forming a plurality of word line trenches crossing the plurality of active regions and extending in parallel with each other in a first horizontal direction, and a plurality of gate dielectric layers and a plurality of word lines to fill the plurality of word line trenches;

forming a plurality of bit line structures each comprising a bit line and an insulating capping line covering the bit line on the substrate, the plurality of bit line structures extending in parallel with each other in a second horizontal direction crossing the first horizontal direction, and a plurality of insulating spacer structures covering opposite sidewalls of each of the bit line structures;

forming a first preliminary buried contact material layer to fill a first space between a pair of insulating spacer structures among the plurality of insulating spacer structures, the pair of insulating spacer structures facing each other across the first space;

removing an upper portion of the first preliminary buried contact material layer to form a second preliminary buried contact material layer and a second space between the pair of insulating spacer structures;

forming a mold layer to fill the second space;

forming a plurality of mold patterns and a plurality of buried contacts by patterning the mold layer and the second preliminary buried contact material layer, respectively,

wherein the plurality of mold patterns are separated from each other and the plurality of buried contacts are separated from each other, and

wherein each of the plurality of buried contacts is connected to a corresponding active region of the plurality of active regions;

forming, after removing the plurality of mold patterns, a plurality of landing pads on the plurality of buried contacts,

wherein each of the plurality of landing pads is connected to a corresponding one of the plurality of buried contacts; and

forming a plurality of capacitors on the plurality of landing pads,

wherein each of the plurality of capacitors includes a bottom electrode connected to a corresponding landing pad of the plurality of landing pads.

16. The method of claim 15 , further comprising:

removing an upper portion of each of the plurality of insulating spacer structures to expose an upper portion of the insulating capping line of each of the plurality of bit line structures, and

forming an expansion capping layer including an upper portion covering the exposed upper portion of the insulating capping line and a bottom portion protruding toward a top surface of the second preliminary buried contact material layer,

wherein the removing of the upper portion of each of the plurality of insulating spacers structures and the forming of the expansion capping layer is performed after removing of the upper portion of the first preliminary buried contact material layer and before the forming of the mold layer.

17. The method of claim 16 , wherein

the expansion capping layer is formed to include a first portion with a first thickness and a second portion with a second thickness smaller than the first thickness, the first portion closer to a top end of the insulating capping line than the second portion.

18. The method of claim 17 , wherein

each of the plurality of landing pads is formed to extend to a top surface of the expansion capping layer.

19. The method of claim 15 ,

wherein each of the plurality of buried contacts and a corresponding one of the plurality of mold patterns connected thereto have a first width and a second width different from the first width, respectively.

20. The method of claim 19 , wherein

wherein the second width is smaller than the first width by about 1 nm to about 5 nm.