3D chip sharing power interconnect layer
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.
1. A three-dimensional (3D) circuit comprising:
a first integrated circuit (IC) die comprising a first set of interconnect layers; and
a second IC die face-to-face mounted with the first IC die and comprising a second set of interconnect layers, wherein at least the top interconnect layer of each of the first and second IC dies comprises clock interconnect segments and power interconnect segments to define a power distribution network and a clock distribution network for the first and second IC dies.
2. The 3D circuit of claim 1 , wherein the clock distribution network is a clock tree.
3. The 3D circuit of claim 2 , wherein
the top interconnect layer of the first die comprises clock interconnect segments along a first direction,
the top interconnect layer of the second die comprises clock interconnect segments along a second direction orthogonal to the first direction, and
to form the clock distribution network, the clock interconnect segments on the first die are connected to clock interconnect segments on the second die through connections that cross a bonding layer that is used to face-to-face mount the first and second IC dies.
4. The 3D circuit of claim 3 , wherein the clock tree is an H-tree.
5. The 3D circuit of claim 1 , wherein the power distribution network is a power mesh.
6. The 3D circuit of claim 5 , wherein
the top interconnect layer of the first die comprises power interconnect segments along a first direction,
the top interconnect layer of the second die comprises power interconnect segments along a second direction orthogonal to the first direction, and
to form the power distribution network, the power interconnect segments on the first die are connected to power interconnect segments on the second die through connections that cross a bonding layer that is used to face-to-face mount the first and second IC dies.
7. The 3D circuit of claim 6 , wherein both the top interconnect layers of first and second IC dies comprise alternating power and ground interconnect segments, and the connections electrically couple power interconnect segments on the first die to power interconnect segments on the second die, and ground interconnect segments on the first die to ground interconnect segments on the second die.
8. The 3D circuit of claim 1 , wherein the clock interconnect segments on the top interconnect layers of the first and second IC dies are shielded from signals outside of the 3D circuit as places the clock interconnect segments are within the interior of an interconnect layer vertical stack formed by the first and second sets of interconnect layers.
9. The 3D circuit of claim 8 , wherein the clock interconnect segments are further shielded by the power interconnect segments on the top interconnect layers of the first and second IC dies.
10. The 3D circuit of claim 1 , wherein the interconnect segments on the top interconnect layers of the first and second IC dies are thicker and wider than interconnect segments on a first plurality of lower interconnect layers of the first and second IC dies.
11. An electronic device comprising:
a three-dimensional (3D) circuit comprising:
a first integrated circuit (IC) die comprising a first set of interconnect layers; and
a second IC die face-to-face mounted with the first IC die and comprising a second set of interconnect layers, wherein at least the top interconnect layer of each of the first and second IC dies comprises clock interconnect segments and power interconnect segments to define a power distribution network and a clock distribution network for the first and second IC dies; and
a substrate on which the 3D circuit is mounted.
12. The electronic device of claim 11 , wherein the clock distribution network is a clock tree.
13. The electronic device of claim 12 , wherein
the top interconnect layer of the first die comprises clock interconnect segments along a first direction,
the top interconnect layer of the second die comprises clock interconnect segments along a second direction orthogonal to the first direction, and
to form the clock distribution network, the clock interconnect segments on the first die are connected to clock interconnect segments on the second die through connections that cross a bonding layer that is used to face-to-face mount the first and second IC dies.
14. The electronic device of claim 13 , wherein the clock tree is an H-tree.
15. The electronic device of claim 11 , wherein the power distribution network is a power mesh.
16. The electronic device of claim 15 , wherein
the top interconnect layer of the first die comprises power interconnect segments along a first direction,
the top interconnect layer of the second die comprises power interconnect segments along a second direction orthogonal to the first direction, and
to form the power distribution network, the power interconnect segments on the first die are connected to power interconnect segments on the second die through connections that cross a bonding layer that is used to face-to-face mount the first and second IC dies.
17. The electronic device of claim 16 , wherein both the top interconnect layers of first and second IC dies comprise alternating power and ground interconnect segments, and the connections electrically couple power interconnect segments on the first die to power interconnect segments on the second die, and ground interconnect segments on the first die to ground interconnect segments on the second die.
18. The electronic device of claim 11 , wherein the clock interconnect segments on the top interconnect layers of the first and second IC dies are shielded from signals outside of the 3D circuit as the clock interconnect segments are within the interior of an interconnect layer vertical stack formed by the first and second sets of interconnect layers.
19. The electronic device of claim 18 , wherein the clock interconnect segments are further shielded by the power interconnect segments on the top interconnect layers of the first and second IC dies.
20. The electronic device of claim 11 , wherein the interconnect segments on the top interconnect layers of the first and second IC dies are thicker and wider than interconnect segments on a first plurality of lower interconnect layers of the first and second IC dies.