IP Library › Granted Patent US 11,901,248
Granted Patent B2
US 11,901,248 · App. 16/832,851 · Granted Feb 13, 2024

Embedded die architecture and method of making

Inventors: Robert L. Sankman (Phoenix, AZ); Rahul N. Manepalli (Chandler, AZ); Robert Alan May (Chandler, AZ); Srinivas Venkata Ramanuja Pietambaram (Chandler, AZ); Bharat P. Penmecha (Chandler, AZ)
Assignee: Intel Corporation
H01L23/15H01L21/486H01L23/3128H01L23/5381H01L23/5384H01L25/0655
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Quick Facts
Patent No.
US 11,901,248
App. No.
16/832,851
Granted
Feb 13, 2024
Kind
B2
Abstract

Various examples provide a semiconductor patch. The patch includes a glass core having first and second opposed major surfaces extending in an x-y direction. The patch further includes a conductive via extending from the first major surface to the second major surface substantially in a z-direction. The patch further includes a bridge die embedded in a dielectric material in communication with the conductive via. The patch further includes an overmold at least partially encasing the glass core.

Claims (41)

1. A semiconductor package, comprising:

a package substrate;

a glass core;

an insulator material at least partially encasing the glass core, wherein, along a direction perpendicular to a first surface of the glass core, a portion of the insulator material is between the glass core and the package substrate, and wherein a first surface of the package substrate is closer to the first surface of the glass core than a second surface of the package substrate;

a conductive via extending between the first surface of the glass core and a second surface of the glass core substantially in the direction perpendicular to the first surface of the glass core;

a bridge die in a recess in the package substrate and electrically coupled with the conductive via; and

an electronic component coupled to an end of the conductive via at the second surface of the package substrate.

2. The semiconductor package of claim 1 , wherein the glass core comprises a soda-lime glass, borosilicate glass, alumino-silicate glass, alkali-borosilicate glass, aluminoborosilcate glass, an alkalialuminosilicate glass, or a mixture thereof.

3. The semiconductor package of claim 1 , wherein the glass core comprises a monolithic glass core or a laminate glass core.

4. The semiconductor package of claim 1 , wherein a Coefficient of Thermal Expansion (CTE) of the glass core is between about 3 and about 12.

5. The semiconductor package of claim 1 , wherein the conductive via comprises a conductive material.

6. The semiconductor package of claim 1 , further comprising a solder ball at the second surface of the package substrate, and an interconnect electrically connected to the solder ball and to the electronic component, wherein the solder ball is in conductive contact with the end of the conductive via at the second surface of the package substrate.

7. The semiconductor package of claim 6 , wherein the interconnect is a via.

8. The semiconductor package of claim 1 , wherein a first surface of the bridge die is closer to the glass core than a second surface of the bridge die, the semiconductor package further includes a solder ball at the second surface of the bridge die and an interconnect electrically connected to the solder ball and to the electronic component, and the solder ball is in conductive contact with a conductive pathway in the bridge die.

9. The semiconductor package of claim 1 , wherein the package substrate includes a dielectric material, and the conductive via extends through the dielectric material.

10. The semiconductor package of claim 9 , wherein the dielectric material is in contact with the portion of the insulator material between the glass core and the package substrate.

11. The semiconductor package of claim 9 , wherein the dielectric material includes at least one of an organic based build up film, glass-reinforced epoxy, polytetrafluorethylene, cotton-paper reinforced epoxy, phenolic-glass, paper-phenolic, polyester-glass, or an epoxy mold compound.

12. The semiconductor package of claim 1 , wherein a thickness of the glass core is greater than 1.2 millimeters.

13. A method of forming a semiconductor package, the method comprising:

providing a package substrate;

providing a glass core;

providing an insulator material at least partially encasing the glass core, wherein, along a direction perpendicular to a first surface of the glass core, a portion of the insulator material is between the glass core and the package substrate, and wherein a first surface of the package substrate is closer to the first surface of the glass core than a second surface of the package substrate;

providing a conductive via extending between the first surface of the glass core and a second surface of the glass core substantially in the direction perpendicular to the first surface of the glass core;

providing a bridge die in a recess in the package substrate and electrically coupled with the conductive via; and

providing an electronic component coupled to an end of the conductive via at the second surface of the package substrate.

14. The method of claim 13 , further comprising:

providing a solder ball at the second surface of the package substrate; and

providing an interconnect electrically connected to the solder ball and to the electronic component,

wherein the solder ball is in conductive contact with the end of the conductive via at the second surface of the package substrate.

15. The method of claim 13 , wherein the glass core comprises a soda-lime glass, borosilicate glass, alumino-silicate glass, alkali-borosilicate glass, aluminoborosilcate glass, an alkalialuminosilicate glass, or a mixture thereof.

16. A semiconductor package, comprising:

a package substrate having a first surface and a second surface, opposite the first surface;

a bridge die in a cavity in the second surface of the package substrate;

a further die above the package substrate;

one or more electrically conductive interconnects between the bridge die and the further die;

a glass core having a through-opening between a first surface of the glass core and a second surface of the glass core, wherein the first surface of the glass core is closer to the package substrate than the second surface of the glass core; and

a conductive via extending between the second surface of the glass core and the second surface of the package substrate, wherein a first portion of the conductive via extends through the through-opening of the glass core and a second portion of the conductive via extends through the package substrate.

17. The semiconductor package of claim 16 , further comprising a dielectric material at least partially enclosing the glass core, wherein a portion of the dielectric material is between the glass core and the package substrate, and a third portion of the conductive via extends through the dielectric material.

18. The semiconductor package of claim 17 , wherein, along a direction perpendicular to the first surface of the glass core, the third portion is between the first portion and the second portion.

19. The semiconductor package of claim 17 , wherein the dielectric material fully encloses the glass core.

20. The semiconductor package of claim 16 , wherein a thickness of the glass core is greater than 1.2 millimeters.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2020
From: SANKMAN, ROBERT L.; MANEPALLI, RAHUL N.; MAY, ROBERT ALAN; PIETAMBARAM, SRINIVAS VENKATA RAMANUJA; PENMECHA, BHARAT P.
To: INTEL CORPORATION
Reel/Frame 054573/0748 →
Continuity (1)
Related Publication 20210305108A1 · Sep 30, 2021
Cited By (1)
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