IP Library › Granted Patent US 10,977,762
Granted Patent B2
US 10,977,762 · App. 16/834,902 · Granted Apr 13, 2021

Handling pipeline submissions across many compute units

Inventors: Balaji Vembu (Folsom, CA); Altug Koker (El Dorado Hills, CA); Joydeep Ray (Folsom, CA)
Assignee: Intel Corporation
G06T1/20G06T15/005G06T2200/04
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Quick Facts
Patent No.
US 10,977,762
App. No.
16/834,902
Granted
Apr 13, 2021
Kind
B2
Abstract

One embodiment provides for a general-purpose graphics processing unit multiple processing elements having a single instruction, multiple thread (SIMT) architecture configured to perform hardware multithreading during execution of a plurality of thread groups. The plurality of thread groups can include one or more sub-groups of threads, with a first sub-group is associated with a first thread group and a second sub-group associated with a second thread group. Data dependencies can be used to trigger the launch of threads, such that when a first thread in the second sub-group has a data dependency upon a first thread in the first sub-group, circuitry in the general-purpose graphics processing unit can launch at least the first thread in the second sub-group to execute in response to satisfaction of the data dependency.

Claims (42)

1. A general purpose graphics processing unit comprising:

multiple processing elements having a single instruction, multiple thread (SIMT) architecture, the multiple processing elements to perform hardware multithreading during execution of a plurality of thread groups,

wherein the plurality of thread groups includes one or more sub-groups of threads;

wherein a first sub-group is associated with a first thread group and a second sub-group is associated with a second thread group, and

wherein a first thread in the second sub-group has a data dependency upon a first thread in the first sub-group; and

circuitry to include hardware or firmware to launch at least the first thread in the second sub-group to execute in response to satisfaction of the data dependency.

2. The general purpose graphics processing unit of claim 1 , further including a scheduler, the scheduler to schedule one or more threads of the first sub-group to execute concurrently with one or more threads of the second sub-group.

3. The general purpose graphics processing unit of claim 1 , wherein the second thread group includes 8 sub-groups, the 8 sub-groups including the second sub-group.

4. The general purpose graphics processing unit of claim 3 , wherein the circuitry is to independently retire thread sub-groups of the second thread group.

5. The general purpose graphics processing unit of claim 4 , wherein the circuitry is to retire one or more threads of the second sub-group associated with the second thread group and launch at least one thread of a third thread group associated with the second thread group.

6. The general purpose graphics processing unit of claim 1 , wherein a number of threads in at least one of the sub-groups is a power of 2.

7. The general purpose graphics processing unit of claim 1 , wherein a number of threads in a first sub-group is equal to 32 and a number of threads in a second sub-group is equal to 4.

8. A method comprising:

on a general purpose graphics processing unit having a single instruction, multiple thread (SIMT) architecture:

performing hardware multithreading during execution of a plurality of thread groups, at least two of the plurality of thread groups including one or more sub-groups, wherein a first sub-group is associated with a first thread group, a second sub-group is associated with a second thread group, and a first thread in the second sub-group has a data dependency upon a first thread in the first sub-group; and

launching at least the first thread in the second sub-group in response to satisfaction of the data dependency.

9. The method of claim 8 , additionally comprising executing one or more threads of the first sub-group concurrently with one or more threads of the second sub-group.

10. The method of claim 9 , additionally comprising checking at least one data dependency of multiple threads within the second sub-group and launching the multiple threads of the second sub-group in response to satisfaction of the at least one data dependency.

11. The method of claim 10 , wherein the second thread group includes 8 sub-groups, the 8 sub-groups including the second sub-group.

12. The method of claim 11 , additionally comprising independently retiring thread sub-groups of the second thread group.

13. The method of claim 12 , additionally comprising retiring one or more threads the second sub-group of the second thread group and launching at least one thread of a third thread group of the second thread group.

14. A graphics processing system comprising:

a general purpose graphics processing unit including:

multiple processing elements having a single instruction, multiple thread (SIMT) architecture, the multiple processing elements to perform hardware multithreading during execution of a plurality of thread groups wherein the plurality of thread groups includes one or more sub-groups of threads, a first sub-group is associated with a first thread group, a second sub-group is associated with a second thread group, and a first thread in the second sub-group has a data dependency upon a first thread in the first sub-group; and

a logic unit to include hardware or firmware logic, the logic unit to launch at least the first thread in the second sub-group to execute in response to satisfaction of the data dependency; and

a memory coupled with the general purpose graphics processing unit.

15. The graphics processing system of claim 14 , further including a scheduler, the scheduler to schedule one or more threads of the first sub-group to execute concurrently with one or more threads of the second sub-group.

16. The graphics processing system of claim 14 , wherein the second thread group includes 8 sub-groups, the 8 sub-groups including the second sub-group.

17. The graphics processing system of claim 16 , wherein the logic unit is to independently retire thread sub-groups of the second thread group.

18. The graphics processing system of claim 17 , wherein the logic unit is to retire one or more threads the second sub-group of the second thread group and launch at least one thread of a third thread group of the second thread group.

19. The graphics processing system of claim 14 , wherein a number of threads in at least one of the sub-groups is a power of 2.

20. The graphics processing system of claim 14 , wherein a number of threads in a first sub-group is equal to 32 and a number of threads in a second sub-group is equal to 4.

21. A general-purpose graphics processing device comprising:

multiple processing elements; and

a logic unit to include hardware or firmware logic, the logic unit to:

launch threads of a first thread group on the multiple processing elements,

wherein to launch the threads of the first thread group includes to distribute threads of the first thread group as multiple sub-groups;

manage execution of the multiple sub-groups of the first thread group;

retire a first sub-group of the first thread group;

group active threads for execution on the multiple processing elements; and

launch a second sub-group of the first thread group, wherein the second sub-group is to execute concurrently with a third sub-group from a second thread group, a first thread in the second sub-group has a data dependency upon a first thread in the first sub-group and the logic unit is to launch at least the first thread in the second sub-group in response to satisfaction of the data dependency.

22. The general-purpose graphics processing device as in claim 21 , wherein the logic unit to independently retire thread sub-groups of the second thread group.

Continuity (4)
Continuation 16446946 · Jun 20, 2019
Continuation 16150012 · Oct 2, 2018
Continuation 15493233 · Apr 21, 2017
Related Publication 20200258186A1 · Aug 13, 2020