Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials. The first oxide layer is in direct contact with the isolation layer.
1. A semiconductor device structure, comprising:
an isolation layer formed over a substrate;
a plurality of nanostructures formed over the isolation layer;
a gate structure wrapped around the nanostructures;
an S/D structure wrapped around the nanostructures; and
a first oxide layer between the substrate and the S/D structure, wherein the first oxide layer and the isolation layer are made of different materials, and the first oxide layer is in direct contact with the isolation layer, and a top surface of the first oxide layer is higher than a bottommost surface of the nanostructures.
2. The semiconductor device structure as claimed in claim 1 , further comprising:
an inner spacer between the gate structure and the S/D structure, wherein the inner spacer and the isolation layer are made of the same material.
3. The semiconductor device structure as claimed in claim 2 , wherein the inner spacer has a C-shaped structure with a recessed central portion, and a second oxide layer is formed in the recessed central portion.
4. The semiconductor device structure as claimed in claim 3 , wherein the second oxide layer is in direct contact with the S/D structure.
5. The semiconductor device structure as claimed in claim 1 , wherein the first oxide layer is in direct contact with one of the nanostructures.
6. The semiconductor device structure as claimed in claim 1 , wherein an interface between the first oxide layer and the S/D structure is substantially level with or higher than a top surface of the isolation layer.
7. The semiconductor device structure as claimed in claim 1 , wherein a top surface of the first oxide layer is higher than a bottommost surface of the gate structure.
8. A semiconductor device structure, comprising:
an isolation layer formed over a substrate;
a plurality of nanostructures formed over the isolation layer;
a gate structure wrapped around the nanostructure;
an S/D structure wrapped around the nanostructure;
an inner spacer between the gate structure and the S/D structure, wherein the inner spacer comprises a recessed portion; and
a first oxide layer formed in the recessed portion of the inner spacer, wherein the first oxide layer and the inner spacer are made of different materials.
9. The semiconductor device structure as claimed in claim 8 , wherein the first oxide layer is in direct contact with the S/D structure.
10. The semiconductor device structure as claimed in claim 8 , wherein the first oxide layer is between the S/D structure and the inner spacer.
11. The semiconductor device structure as claimed in claim 8 , further comprising:
a second oxide layer between the substrate and the S/D structure, wherein the second oxide layer and the isolation layer are made of different materials, and the second oxide layer is in direct contact with the isolation layer.
12. The semiconductor device structure as claimed in claim 11 , wherein the second oxide layer is between one of the nanostructures and the substrate.
13. The semiconductor device structure as claimed in claim 11 , wherein an interface between the second oxide layer and the S/D structure is higher than a bottom surface of the gate structure.
14. The semiconductor device structure as claimed in claim 8 , wherein the isolation layer and inner spacer are made of the same material, and the isolation layer is directly below the inner spacer.
15. A semiconductor device structure, comprising:
an isolation layer formed over a substrate;
a fin structure formed over an isolation structure;
a plurality of nanostructures formed over the fin structure;
a gate structure wrapped around the nanostructure;
an inner spacer adjacent to the gate structure;
an S/D structure adjacent to the inner spacer; and
a first oxide layer directly below the S/D structure, wherein an interface between the S/D structure and the first oxide layer is in direct contact with a bottommost nanostructure, and a portion of the S/D structure is lower than a top surface of the first oxide layer.
16. The semiconductor device structure as claimed in claim 15 , wherein the inner spacer has a recessed portion, a second oxide layer is formed in the recessed portion, and the first oxide layer and the second oxide layer are made of the same material.
17. The semiconductor device structure as claimed in claim 15 , further comprising:
a liner layer formed on a sidewall of the fin structure, wherein the liner layer is in direct contact with the first oxide layer.
18. The semiconductor device structure as claimed in claim 15 , further comprising:
a seal spacer adjacent to the gate structure; and
a dielectric layer adjacent to the seal spacer, wherein the dielectric layer is in direct contact with the inner spacer.
19. The semiconductor device structure as claimed in claim 15 , wherein a top surface of the first oxide layer is higher than a top surface of the isolation layer.
20. The semiconductor device structure as claimed in claim 1 , wherein a portion of the S/D structure is lower than a top surface of the first oxide layer.