IP Library Granted Patent US 11,096,270
Granted Patent B2
US 11,096,270 · App. 16/837,222 · Granted Aug 17, 2021

Backplane footprint for high speed, high density electrical connectors

Inventors: Marc Robert Charbonneau (Bedford, NH); Jose Ricardo Paniagua (Newmarket, NH)
Assignee: Amphenol Corporation
H05K1/0225H05K1/0219H05K1/0251H05K1/115H05K3/429H05K2201/0723H05K2201/096H05K2201/09727H05K2201/09845
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Quick Facts
Patent No.
US 11,096,270
App. No.
16/837,222
Granted
Aug 17, 2021
Kind
B2
Abstract

A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including a signal layer; and via patterns formed in the plurality of layers, each of the via patterns comprising first and second signal vias extending from a first surface of the printed circuit board to the signal layer, the signal layer including first and second signal traces connected to the first and second signal vias, respectively, the signal layer further including a ground conductor located between the signal traces and adjacent signal-carrying elements.

Claims (8)

1. A printed circuit board comprising:

a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including at least one signal layer; and

via patterns formed in the plurality of layers within a connector footprint of the printed circuit board, wherein the via patterns include a first column of via patterns and a second column of via patterns, wherein each of the via patterns in each of the first and second columns of via patterns includes first and second signal vias and first and second ground vias,

wherein the signal layer includes at least one signal trace between the first column of via patterns and the second column of via patterns, a first conductor located between the first column of via patterns and the at least one signal trace, and a second conductor located between the second column of via patterns and the at least one signal trace, and wherein the first and second conductors are configured for connection to a reference voltage.

2. The printed circuit board as defined in claim 1 , wherein the first conductor and the second conductor each comprise a conductive strip located between the first and second columns of via patterns.

3. The printed circuit board as defined in claim 1 wherein the first conductor and the second conductor each comprise conductive areas that surround the via patterns of the first and second columns of via patterns.

4. The printed circuit board as defined in claim 1 wherein the first conductor and the second conductor each comprise a copper conductor configured for connection to ground.

5. The printed circuit board as defined in claim 1 wherein the at least one signal trace comprises first and second signal traces that form a differential signal pair.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2020
From: CHARBONNEAU, MARC ROBERT; PANIAGUA, JOSE RICARDO
To: AMPHENOL CORPORATION
Reel/Frame 053354/0214 →
Continuity (5)
Division 16223195 · Dec 18, 2018
Division 15807444 · Nov 8, 2017
Continuation In Part 15452096 · Mar 7, 2017
Provisional Application 62305049 · Mar 8, 2016
Related Publication 20200229299A1 · Jul 16, 2020
Cited By (4)
US 1,067,191 US 1,068,685 US 12,207,395 US 12,309,915