Gate structure and photomask of NAND memory and method for making the same
View Patent ↗A method for forming the gate structure of the NAND memory, comprising the steps of disposing a gate structure layer, a pattern transfer layer, a TEOS structure, and an organic dielectric Tri-Layer on a substrate sequentially; performing a patterning using a first photomask and a first photoresist layer; performing an etching process to form a control gate structure, a peripheral gate structure and a select gate structure; performing a trimming process to them; patterning sidewalls on sides of them; performing a second patterning using a second photomask as a mask and a second photoresist layer to protect the peripheral gate structure, the select gate structure, and their sidewalls; removing the control gate structure between its sidewalls; performing etching by using the sidewalls, the peripheral gate structure and the select gate structure as masks to form the control gate, the peripheral gate, and the select gate.
1. A method for manufacturing a gate structure of an NAND memory, comprising the steps of:
S1: providing a substrate, disposing a gate structure layer, a pattern transfer layer, a tetraethyl orthosilicate (TEOS) structure, and an organic dielectric Tri-Layer on the substrate sequentially;
S2: performing a first-pass photolithography process by using a first photomask and a first photoresist layer in the organic dielectric Tri-Layer;
S3: performing an etching process to the organic dielectric Tri-Layer and the TEOS structure, removing the organic dielectric Tri-Layer to form a control gate structure, a peripheral gate structure and a select gate structure;
S4: performing a trimming process to the control gate structure, the peripheral gate structure, and the select gate structure;
S5: patterning sidewalls on sides of the control gate structure, the peripheral gate structure, and the select gate structure;
S6: performing a second-pass photolithography process by using a second photomask as a mask and a second photoresist layer to protect the peripheral gate structure, the select gate structure, and the sidewalls on sides of the peripheral gate structure and the select gate structure;
S7: removing the control gate structure between its sidewalls; and
S8: performing etching by using the sidewalls, the peripheral gate structure and the select gate structure as masks to form the control gate, the peripheral gate, and the select gate.
2. The method for forming the gate structure of the NAND memory according to claim 1 , wherein the gate structure layer comprises a silicon oxide layer, a floating gate layer, a silicon oxide layer-silicon nitride-silicon oxide layer, and a control gate layer.
3. The method for forming the gate structure of the NAND memory according to claim 1 , wherein the pattern transfer layer comprises a silicon nitride layer, a silicon oxide layer, and an amorphous silicon layer.
4. The method for forming the gate structure of the NAND memory according to claim 1 , wherein the TEOS structure comprises a silicon oxide film layer comprising a TEOS layer and a high-temperature oxide layer.
5. The method for forming the gate structure of the NAND memory according to claim 1 , wherein the organic dielectric Tri-Layer comprises an organic dielectric layer, a silicon-containing anti-reflection layer and the first photoresist layer.
6. The method for forming the gate structure of the NAND memory according to claim 1 , wherein in step S3, each of a width of the peripheral gate structure and a width of the select gate structure is larger than a width of the control gate structure.
7. The method for forming the gate structure of the NAND memory according to claim 1 , wherein in step S3, the select gate structure is adjacent to the control gate structure.
8. The method for forming the gate structure of the NAND memory according to claim 6 , wherein in step S3, each of the width of the peripheral gate structure and the width of the select gate structure is larger than the width of the control gate structure.
9. The method for forming the gate structure of the NAND memory according to claim 1 , wherein in step S3, the select gate structure is adjacent to the control gate structure.
10. The method for forming the gate structure of the NAND memory according to claim 6 , wherein in step S4, each of the width of the control gate structure, the width of the peripheral gate structure and the width of the select gate structure is reduced.
11. The method for forming the gate structure of the NAND memory according to claim 1 , wherein in step S5, the sidewalls of the select gate structure is adjacent to the sidewalls of the control gate structure.
12. The method for forming the gate structure of the NAND memory according to claim 1 , wherein in step S6, the second photoresist layer is patterned to be on the peripheral gate structure and the select gate structure.
13. The method for forming the gate structure of the NAND memory according to claim 6 , wherein the widths of all sidewall structures of the control gate structures are the same.
14. An NAND memory, comprising a control gate, a select gate and a peripheral gate fabricated by adopting the method for forming the gate structure of the NAND memory according to claim 1 .