Charge transfer circuit for compact modulators
The present disclosure provides a current generation circuit. In one aspect, the circuit includes a current source transistor and a current sink transistor connected to the current source transistor in series, with respective sources of the current source and sink transistors being connected with each other at a common node. A voltage difference between respective gates of the current source and sink transistors defines a current value flowing through the series, the voltage difference being variable such that the current value is either time-dependent or time-independent. Respective drains of the current source and sink transistors provide a high resistance output necessary to provide a current source or sink function thereby rejecting influence of drain variation or error on the current value.
1. A current generation circuit, comprising:
a current source transistor; and
a current sink transistor connected to the current source transistor in series, with respective source terminals of the current source and sink transistors being connected with each other at a common node;
wherein a voltage difference between respective gate terminals of the current source and sink transistors defines a current value flowing through the series, the voltage difference being variable such that the current value is either time-dependent or time-independent;
wherein respective drain terminals of the current source and sink transistors provide a high resistance output necessary to provide a current source or sink function, thereby rejecting influence of drain variation or error on the current value; and
wherein one of the drain terminals of the series of the current source and sink transistors is connected to a current input.
2. The circuit of claim 1 , further comprising:
a transistor switch connected between the current input and said one of the drain terminals of the series of the current source and sink transistors to control either a source current or a sink current with a time-varying signal; and
a supply voltage connected to the other one of the drain terminals of the series of the current source and sink transistors so as to provide charge flow.
3. The circuit of claim 2 , wherein charge memory associated with the common node is set through manipulation of a gate voltage of the transistor switch between time varying current pulse events.
4. The circuit of claim 2 , wherein charge memory associated with the common node is set using at least a reset element connected between the common node and the supply voltage.
5. The circuit of claim 2 , wherein an amount of charge transferred through the series is set by both the time-varying signal and the voltage difference.
6. A delta-sigma modulator, containing the circuit of claim 1 .
7. An analog counter circuit for increment or decrement counting, containing the circuit of claim 1 .
8. A prioritizing and weighting circuit containing the circuit of claim 1 .
9. An array of repetitive circuits containing the circuit of claim 1 , the array of repetitive circuits being configured to process signals from sensing transducers.
10. The array of claim 9 , wherein the signals are processed using Delta-Sigma Modulation.
11. The array of claim 9 , wherein the sensing transducers comprise photon-sensitive detectors.
12. An array of repetitive circuits containing the circuit of claim 1 , the array of repetitive circuits being configured to process signals from at least one of a comparator, an amplifier, a feedback circuit, a memory circuit, a neighboring circuit, an external array of repetitive circuits, a controller, a pattern generator, and an analog arithmetic logic unit.
13. The circuit of claim 1 , wherein the current source transistor comprises a p-type transistor and the current sink transistor comprises an n-type transistor.
14. The circuit of claim 9 , wherein the p-type and n-type transistors are MOSFET.
15. A current generation circuit, comprising:
a current source transistor;
a current sink transistor connected to the current source transistor in series, with respective source terminals of the current source and sink transistors being connected with each other at a common node; and
first and second transistor switches each being connected to a respective one of drain terminals of the series of the current source and sink transistors, such that either a source current or a sink current is utilized through selectable and time-varying input control signals sent to the first and second transistor switches;
wherein a voltage difference between respective gate terminals of the current source and sink transistors defines a current value flowing through the series, the voltage difference being variable such that the current value is either time-dependent or time-independent;
wherein respective drain terminals of the series of the current source and sink transistors provide a high resistance output necessary to provide a current source or sink function, thereby rejecting influence of drain variation or error on the current value; and
wherein at least one of the drain terminals of the series of the current source and sink transistors is connected to a current input through a respective one of the first and second transistor switches.
16. The circuit of claim 15 , wherein charge memory associated with the common node is set through manipulation of a gate voltage of the first and second transistor switches between time varying current pulse events.
17. The circuit of claim 15 , wherein an amount of charge transferred through the series is set by both the time-varying input control signal and the voltage difference.
18. The circuit of claim 15 , wherein charge memory associated with the common node is set using at least a reset element connected between the common node and a supply voltage connected to the other one of the drain terminals of the series of the current source and sink transistors.
19. A delta-sigma modulator, containing the circuit of claim 15 .
20. An analog counter circuit for increment or decrement counting, containing the circuit of claim 15 .
21. A prioritizing and weighting circuit containing the circuit of claim 15 .
22. An array of repetitive circuits containing the circuit of claim 12 , the array of repetitive circuits being configured to process signals from sensing transducers.
23. The array of claim 22 , wherein the signals are processed using Delta-Sigma Modulation.
24. The array of claim 22 , wherein the sensing transducers comprise photon-sensitive detectors.
25. An array of repetitive circuits containing the circuit of claim 15 , the array of repetitive circuits being configured to process signals from at least one of a comparator, an amplifier, a feedback circuit, a memory circuit, a neighboring circuit, an external array of repetitive circuits, a controller, a pattern generator, and an analog arithmetic logic unit.
26. The circuit of claim 15 , wherein the current source transistor comprises a p-type transistor and the current sink transistor comprises an n-type transistor.
27. The circuit of claim 26 , wherein the p-type and n-type transistors are MOSFET.