Adaptive charge measurement circuit for data converters
Data converter circuits and methods of operating the data converter circuits are disclosed. In some embodiments, a data converter circuit includes a charge measurement circuit. In some embodiments, the charge measurement circuit is a capacitive transimpedance amplifier (CTIA). In some embodiments, the data converter circuit includes the CTIA, a quantizer, a digital-to-analog converter, a summer, and a digital filter. In some embodiments, the data converter circuit includes an analog-to-digital converter electrically coupled to the CTIA and the digital filter. In some embodiment, a method includes integrating an input signal with a CTIA, determining whether a CTIA output signal is greater than a threshold, and reducing the CTIA output signal or forgoing the reducing based on the determination of whether the CTIA output signal is greater than the threshold.
1. A circuit, comprising:
an analog input electrically coupled to a sensor;
a charge transimpedance amplifier (CTIA) electrically coupled to the analog input,
wherein the CTIA comprises a feedback capacitor, and
wherein a capacitance of the feedback capacitor is smaller than a capacitance of the sensor;
a quantizer electrically coupled to an output of the CTIA;
a digital-to-analog converter (DAC) electrically coupled to an output of the quantizer;
a summer electrically coupled to an output of the DAC, wherein the CTIA is electrically coupled to an output of the summer;
a digital filter electrically coupled to the output of the quantizer; and
a digital output electrically coupled to the digital filter.
2. The circuit of claim 1 , wherein the summer is configured to cause a CTIA output signal to be reduced in response to receiving a high DAC output signal at the output of the DAC.
3. The circuit of claim 1 , wherein:
the quantizer is configured to:
determine whether a CTIA output signal at the output of the CTIA is greater than a threshold;
in accordance with a determination that the CTIA output signal is greater than the threshold, output a first digital value to the DAC; and
in accordance with a determination that the CTIA output signal is not greater than the threshold, output a second digital value to the DAC, and the DAC is configured to:
in response to receiving the first digital value, output a high DAC output signal to the summer; and
in response to receiving the second digital value, forgo outputting the high DAC output signal to the summer.
4. The circuit of claim 1 , further comprising an analog-to-digital converter (ADC) electrically coupled to the output of the CTIA, wherein:
the ADC is configured to:
receive a voltage corresponding to a residue charge at the output of the CTIA; and
provide a digital value corresponding to the residue charge, and
the digital output includes the digital value corresponding to the residue charge.
5. The circuit of claim 1 , further comprising an offset removal circuit, wherein the offset removal circuit is configured to remove an offset from a CTIA output signal.
6. The circuit of claim 1 , wherein an ADC is configured to convert an offset from a CTIA output signal into a digital value of the offset.
7. The circuit of claim 1 , further comprising a low-pass filter included in a feedback of the CTIA.
8. The circuit of claim 1 , wherein:
a sensitivity of the circuit is based on a frequency of operation of the circuit, and
the frequency of operation of the circuit is based on an integration time of the CTIA.
9. The circuit of claim 1 , wherein a digital output signal at the digital output is a digital value of a charge at the analog input of the circuit.
10. The circuit of claim 1 , wherein a digital output signal at the digital output is a digital value of a current at the analog input of the circuit.
11. The circuit of claim 1 , wherein a digital output signal at the digital output is a digital value of a voltage at the analog input of the circuit.
12. The circuit of claim 1 , further comprising a variable resistor electrically coupled to the analog input, wherein the variable resistor is configured to reduce a signal level of an input signal at the analog input of the circuit.
13. The circuit of claim 1 , wherein the digital filter includes a Finite Impulse Response (FIR) decimator, wherein:
the FIR decimator is configured to generate a digital output signal at the digital output based on the signals received from the output of the quantizer.
14. The circuit of claim 1 , wherein the quantizer and the DAC are included in a combined quantizer and DAC of the circuit.
15. A method, comprising:
integrating, with a CTIA of a circuit, an input signal;
determining whether a CTIA output signal at the output of the CTIA is greater than a threshold;
in accordance with a determination that the CTIA output signal is greater than the threshold:
reducing the CTIA output signal; and
in accordance with a determination that the CTIA output signal is not greater than the threshold:
forgoing reducing the CTIA output signal.
16. The method of claim 15 , further comprising:
electrically coupling a sensor to the CTIA, wherein:
the sensor provides the input signal,
the CTIA comprises a feedback capacitor, and
a capacitance of the feedback capacitor is smaller than a capacitance of the sensor.
17. The method of claim 15 , further comprising generating a digital output signal corresponding to the input signal.
18. The method of claim 17 , wherein:
the input signal is a charge at an analog input of the circuit, and
the digital output signal is a digital value of the charge.
19. A non-transitory computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by an electronic device with one or more processors and memory, cause the device to perform a method comprising:
integrating, with a CTIA of a circuit, an input signal;
determining whether a CTIA output signal at the output of the CTIA is greater than a threshold;
in accordance with a determination that the CTIA output signal is greater than the threshold:
reducing the CTIA output signal; and
in accordance with a determination that the CTIA output signal is not greater than the threshold:
forgoing reducing the CTIA output signal.