IP Library › Granted Patent US 11,265,010
Granted Patent B2
US 11,265,010 · App. 16/837,417 · Granted Mar 1, 2022

Incremental analog-to-digital converter

Inventors: Yun-Shiang Shu (Hsinchu, TW); Su-Hao Wu (Hsinchu, TW); Hung-Yi Hsieh (Hsinchu, TW); Albert Yen-Chih Chiou (Hsinchu, TW)
Assignee: MEDIATEK INC.
H03M3/422H03M3/464
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,265,010
App. No.
16/837,417
Granted
Mar 1, 2022
Kind
B2
Abstract

An incremental analog-to-digital converter (ADC) with high accuracy. The incremental ADC has a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal, and a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal. A loop filter of the delta-sigma modulator has a preset circuit. In the preset circuit, the output terminal of the loop filter is preset rather than being reset during the reset phase of the incremental ADC.

Claims (55)

1. An incremental analog-to-digital converter, comprising:

a delta-sigma modulator, performing delta-sigma modulation on an analog input signal to output a quantized signal; and

a digital filter, receiving the quantized signal to generate a digital representation of the analog input signal,

wherein:

the delta-sigma modulator includes a quantizer, a digital-to-analog converter, and a loop filter;

the quantizer outputs the quantized signal;

the digital-to-analog converter has an input terminal coupled to an output terminal of the quantizer, and generates an estimate of the quantized signal;

the loop filter operates according to a difference between the analog input signal and the estimate, and an output terminal of the loop filter is coupled to an input terminal of the quantizer;

the loop filter has a preset circuit that presets the output terminal of the loop filter to a value dependent on the analog input signal during a reset phase of the incremental analog-to-digital converter, wherein the quantizer is reset during the reset phase; and

the preset circuit couples the analog input signal to the output terminal of the loop filter during the reset phase.

2. The incremental analog-to-digital converter as claimed in claim 1 , wherein:

the loop filter comprises a plurality of analog integrators cascaded in a series;

the preset circuit includes a plurality of preset elements corresponding to the plurality of analog integrators one by one; and

each preset element and a feedback capacitor of the corresponding analog integrator are connected in parallel during the reset phase of the incremental analog-to-digital converter.

3. The incremental analog-to-digital converter as claimed in claim 1 , wherein:

the loop filter comprises a first analog integrator;

the first analog integrator has a first operational amplifier and a first feedback capacitor coupled between an input terminal and an output terminal of the first operational amplifier;

the preset circuit comprises a first switch and a first preset element connected in series between the input terminal and the output terminal of the first operational amplifier; and

the first switch is closed during the reset phase of the incremental analog-to-digital converter.

4. The incremental analog-to-digital converter as claimed in claim 3 , wherein:

the loop filter further comprises a second analog integrator coupled between the first analog integrator and the quantizer;

the second analog integrator has a second operational amplifier and a second feedback capacitor coupled between an input terminal and an output terminal of the second operational amplifier;

the preset circuit further comprises a second switch and a second preset element connected in series between the input terminal and the output terminal of the second operational amplifier; and

the second switch is closed during the reset phase of the incremental analog-to-digital converter.

5. The incremental analog-to-digital converter as claimed in claim 4 , wherein:

the second analog integrator comprises an input resistor coupled between the output terminal of the first operational amplifier and the input terminal of the second operational amplifier;

the preset circuit further comprises a third switch and a third preset element connected in series between the output terminal of the first operational amplifier and the input terminal of the second operational amplifier; and

the third switch is closed during the reset phase of the incremental analog-to-digital converter.

6. The incremental analog-to-digital converter as claimed in claim 5 , wherein:

the first, second and third preset elements are resistors.

7. The incremental analog-to-digital converter as claimed in claim 1 , wherein:

the loop filter comprises a plurality of analog integrators cascaded in a series;

the preset circuit couples the analog input signal to output terminals of the analog integrators during the reset phase of the incremental analog-to-digital converter.

8. The incremental analog-to-digital converter as claimed in claim 7 , wherein:

the analog integrators are reset during the reset phase of the incremental analog-to-digital converter.

9. The incremental analog-to-digital converter as claimed in claim 7 , wherein:

the analog integrators are switched-capacitor integrators.

10. The incremental analog-to-digital converter as claimed in claim 1 , wherein:

the loop filter comprises a first analog integrator;

the preset circuit comprises a first switch and a first preset element connected in series;

the first switch is closed during the reset phase of the incremental analog-to-digital converter; and

the analog input signal is coupled to an output terminal of the first analog integrator by the first preset element when the first switch is closed.

11. The incremental analog-to-digital converter as claimed in claim 10 , wherein:

the loop filter further comprises a second analog integrator coupled between the first analog integrator and the quantizer;

the preset circuit comprises a second switch and a second preset element connected in series between the output terminal of the first analog integrator and an output terminal of the second analog integrator; and

the second switch is closed during the reset phase of the incremental analog-to-digital converter.

12. The incremental analog-to-digital converter as claimed in claim 11 , wherein:

the first and second analog integrators are reset during the reset phase of the incremental analog-to-digital converter.

13. The incremental analog-to-digital converter as claimed in claim 11 , wherein:

the first and second analog integrators are switched-capacitor integrators.

14. The incremental analog-to-digital converter as claimed in claim 1 , wherein:

the digital filter comprises a digital integrator that is reset during the reset phase of the incremental analog-to-digital converter.

15. The incremental analog-to-digital converter as claimed in claim 13 , wherein:

when the first switch is closed, the analog input signal is directly connected to a first terminal of the first preset element and a second terminal of the first preset element is directly connected to the output terminal of the first analog integrator;

when the second switch is closed, the output terminal of the first analog integrator is directly connected to a first terminal of the second preset element and a second terminal of the second preset element is directly connected to the output terminal of the second analog integrator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: SHU, YUN-SHIANG; WU, SU-HAO; HSIEH, HUNG-YI; CHIOU, ALBERT YEN-CHIH
To: MEDIATEK INC.
Reel/Frame 052285/0193 →
Continuity (2)
Provisional Application 62839820 · Apr 29, 2019
Related Publication 20200343905A1 · Oct 29, 2020