Permuting in a matrix-vector processor

1. A matrix-vector permuting system comprising a permute execution circuit that includes:

an input register configured to receive and access vectors of elements of an input matrix, the input register having N addresses for storing each element of the input matrix,

a plurality of multiplexors, wherein each multiplexor is connected to the N addresses of the input register and each output of the plurality of multiplexors is sent to a corresponding value output of the permute execution circuit, and

a control register connected to the plurality of multiplexors, the control register having N addresses, wherein each address is configured to store an element corresponding to a control signal for controlling a permutation of one of the elements of the input matrix.

2. The system of claim 1 , wherein the vectors of elements of the input matrix are received as staggered input and wherein the permute execution circuit further comprises:

a flattening register configured to:

receive each input element of input vector in a separate cycle in an order beginning with a lowest-order bit position of the flattening register; and

pop all input elements of the input vector simultaneously from the flattening register to the input register.

3. The system of claim 2 , wherein each element of the input matrix is received at each cycle in an order beginning with a lowest-order bit position of the input vector.

4. The system of claim 3 , wherein popping all input elements of the input vector simultaneously from the flattening register to the input register comprises:

determining that a highest-order bit of the flattening register has received valid data, and

popping all input elements of the input vector simultaneously from the flattening register to the input register in response to determining that the highest-order bit of the flattening register has received valid data.

5. The system of claim 3 , wherein popping all input elements of the input vector simultaneously from the flattening register to the input register comprises:

determining that the flattening register has received a number of input elements of the input vector equal to a dimension of the input vector, and

popping all input elements of the input vector simultaneously from the flattening register to the input register in response to determining that the flattening register has received the number of input elements of the input vector equal to the dimension of the input vector.

6. The system of claim 1 , wherein the control register is configured to receive a control vector of control elements, and

wherein the permute execution circuit is configured to generate an output vector, comprising:

accessing, at a particular position of the control register, a particular control element of the control vector corresponding to a particular position of the output vector,

selecting a particular position of the input register based on the particular control element of the control vector corresponding to the particular position of the output vector,

accessing, at the particular position of the input register, a particular input element of the input vector, and

outputting the particular input element of the input vector as an output element at the particular position of the output vector.

7. The system of claim 6 , the permute execution circuit further comprising an output register configured to receive the output vector.

8. The system of claim 7 , wherein the output register is configured to output the output vector as a staggered output such that a single output element of the output vector is output at each cycle in an order beginning with a lowest-order bit position of the output vector.

9. A method for matrix-vector permuting, comprising:

receiving and accessing, by an input register of a permuting executing circuit, vectors of elements of an input matrix, the input register having N addresses for storing each element of the input matrix;

connecting each of a plurality of multiplexors to the N addresses of the input register and sending each output of the plurality of multiplexors to a corresponding value output of the permute execution circuit; and

connecting a control register to the plurality of multiplexors, the control register having N addresses, wherein each address is configured to store an element corresponding to a control signal for controlling a permutation of one of the elements of the input matrix.

10. The method of claim 9 , wherein the vectors of elements of the input matrix are received as staggered input by performing operations comprising:

receiving, at a flattening register, each input element of the input vector in a separate cycle in an order beginning with a lowest-order bit position of the flattening register; and

popping, from the flattening register, all input elements of the input vector simultaneously from the flattening register to the input register.

11. The method of claim 10 , wherein the control register is configured to receive a control vector of control elements, and

wherein the permute execution circuit is configured to generate an output vector, comprising:

access, at a particular position of the control register, a particular control element of the control vector corresponding to a particular position of the output vector,

select a particular position of the input register based on the particular control element of the control vector corresponding to the particular position of the output vector,

access, at the particular position of the input register, a particular input element of the input vector, and

output the particular input element of the input vector as an output element at the particular position of the output vector.

12. The method of claim 11 , further comprising an output register configured to receive the output vector.

13. The method of claim 12 , wherein the output register is configured to output the output vector as a staggered output such that a single output element of the output vector is output at each cycle in an order beginning with a lowest-order bit position of the output vector.

14. The method of claim 10 , wherein each element of the input matrix is received at each cycle in an order beginning with a lowest-order bit position of the input vector.

15. The method of claim 14 , wherein popping all input elements of the input vector simultaneously from the flattening register to the input register comprises:

determining that a highest-order bit of the flattening register has received valid data, and

popping all input elements of the input vector simultaneously from the flattening register to the input register in response to determining that the highest-order bit of the flattening register has received valid data.

16. The method of claim 14 , wherein popping all input elements of the input vector simultaneously from the flattening register to the input register comprises:

determining that the flattening register has received a number of input elements of the input vector equal to a dimension of the input vector, and

popping all input elements of the input vector simultaneously from the flattening register to the input register in response to determining that the flattening register has received the number of input elements of the input vector equal to the dimension of the input vector.