Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.
1. A method for fabricating semiconductor device, comprising:
providing a substrate having a first region, a second region, and a third region, wherein the first region comprises an input/output region, the second region comprises a middle gate region, and the third region comprises a core region;
forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region;
forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure;
removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess;
forming a first interfacial layer in the first recess, the second recess, and the third recess after removing the first gate structure, the second gate structure, and the third gate structure;
removing the first interfacial layer in the second recess after forming the first interfacial layer in the first recess, the second recess, and the third recess;
forming a second interfacial layer in the first recess, the second recess, and the third recess;
removing the first interfacial layer and the second interfacial layer in the third recess;
forming a third interfacial layer in first recess, the second recess, and the third recess; and
forming a high-k dielectric layer on the third interfacial layer.
2. The method of claim 1 , wherein the second interfacial layer and the third interfacial layer comprise same material.
3. The method of claim 1 , further comprising:
forming a first work function metal (WFM) layer in the first recess;
forming a second WFM layer in the second recess;
forming a third WFM layer in the third recess; and
forming a low resistance metal layer on the first WFM layer, the second WFM layer, and the third WFM layer.
4. The method of claim 3 , wherein the first WFM layer, the second WFM layer, and the third WFM layer comprise different work functions.
5. The method of claim 4 , wherein the first WFM layer, the second WFM layer, and the third WFM layer comprise different materials.
6. The method of claim 4 , wherein the first WFM layer, the second WFM layer, and the third WFM layer comprise different thicknesses.
7. The method of claim 1 , wherein the first interfacial layer and the second interfacial layer comprise same material.
8. A semiconductor device, comprising:
a substrate having a first region, a second region, and a third region;
a first metal gate on the first region, wherein the first metal gate comprises:
a first interfacial layer;
a high-k dielectric layer on the first interfacial layer; and
a first work function metal (WFM) layer on the high-k dielectric layer;
a second metal gate on the second region, wherein the second metal gate comprises:
the first interfacial layer;
a second interfacial layer on the first interfacial layer;
the high-k dielectric layer on the second interfacial layer; and
a second WFM layer on the high-k dielectric layer, wherein the first WFM layer and the second WFM layer comprise different work functions, each of the first interfacial layer and the second interfacial layer is a single-layered structure, a bottom surface of the first interfacial layer on the first region is even with a bottom surface of the first interfacial layer on the second region, and a thickness of the first interfacial layer on the first region directly contacting the substrate and the high-k dielectric layer and a thickness of the first interfacial layer and the second interfacial layer on the second region directly contacting the substrate and the high-k dielectric layer are different.
9. The semiconductor device of claim 8 , further comprising a third metal gate on the third region, wherein the third metal gate comprises:
the first interfacial layer;
the second interfacial layer on the first interfacial layer;
a third interfacial layer on the second interfacial layer; and
a third WFM layer on the third interfacial layer.
10. The semiconductor device of claim 9 , wherein the first WFM layer, the second WFM layer, and the third WFM layer comprise different work functions.
11. The semiconductor device of claim 10 , wherein the first WFM layer, the second WFM layer, and the third WFM layer comprise different materials.
12. The semiconductor device of claim 10 , wherein the first WFM layer, the second WFM layer, and the third WFM layer comprise different thicknesses.
13. The semiconductor device of claim 8 , wherein the first WFM layer and the second WFM layer comprise different work functions.
14. The semiconductor device of claim 13 , wherein the first WFM layer and the second WFM layer comprise different materials.
15. The semiconductor device of claim 13 , wherein the first WFM layer and the second WFM layer comprise different thicknesses.