Vertical field effect transistor including integrated antifuse
A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
1. An antifuse-integrated vertical field effect transistor (VFET) comprising:
a channel;
a split-channel gate dielectric configured to receive a voltage, the split-channel gate dielectric including a first dielectric layer and a second dielectric layer,
the first dielectric layer having a first thickness, and
the second dielectric layer having a second thickness greater than the first thickness, the second dielectric layer including opposing flanges extending laterally from sidewalls of the channel of the antifuse-integrated VFET,
wherein the antifuse-integrated VFET is configured to selectively invoke a non-programmed mode or a programmed mode based on a state of the first dielectric layer.
2. The antifuse-integrated VFET of claim 1 , wherein the state of the first dielectric layer is configured to change based on the voltage applied to the split-channel gate dielectric.
3. The antifuse-integrated VFET of claim 2 , wherein the antifuse-integrated VFET is configured to invoke the non-programmed mode when the first dielectric layer remains intact in response to receiving the voltage such that the antifuse-integrated vertical FET operates as a metal-oxide-semiconductor (MOS) capacitor, and
wherein the antifuse-integrated VFET is configured to invoke the programmed mode when dielectric breakdown of the first dielectric layer occurs in response to receiving the voltage such that the antifuse-integrated vertical FET operates as a transistor.
4. The antifuse-integrated VFET of claim 3 , wherein the first dielectric layer remains intact when the voltage does not induce the dielectric breakdown of the first dielectric layer.
5. The antifuse-integrated VFET of claim 4 , wherein the antifuse-integrated vertical FET includes a source/drain region.
6. The antifuse-integrated VFET of claim 5 , wherein the antifuse-integrated VFET is configured to inhibit current flow through the source/drain region when operating in the non-programmed mode.
7. The antifuse-integrated VFET of claim 5 , wherein the antifuse-integrated VFET is configured to flow current through the source/drain region in response to inducing the programmed mode.
8. The antifuse-integrated VFET of claim 6 , wherein the current flowing through the source/drain region is equivalent to an on-current of the transistor.
9. The antifuse-integrated VFET of claim 8 , wherein the on-current of the transistor is influenced by the second thickness of the second dielectric layer.
10. The antifuse-integrated VFET of claim 9 , wherein the on-current of the transistor is influenced by the second thickness of the second dielectric layer in response to breaking down the first dielectric layer.
11. The antifuse-integrated VFET of claim 10 , wherein the source/drain region is a bit line.
12. The antifuse-integrated VFET of claim 11 , wherein the bit line is coupled to a memory cell.
13. The antifuse-integrated VFET of claim 3 , wherein the transistor is a MOS diode transistor.
14. The antifuse-integrated VFET of claim 3 , wherein the first dielectric layer comprises a high-dielectric constant (high-k) material.
15. The antifuse-integrated VFET of claim 14 , wherein the high-k material comprises hafnium oxide (HfO 2 ).
16. The antifuse-integrated VFET of claim 15 , wherein the first thickness of the high-k material ranges from 1 nm to 2 nm.
17. The antifuse-integrated VFET of claim 14 , wherein the second dielectric layer comprises a dielectric material different from the high-k dielectric material.
18. The antifuse-integrated VFET of claim 17 , wherein the dielectric material comprises silicon oxide (SiO 2 ).
19. The antifuse-integrated VFET of claim 18 , wherein the second thickness of the dielectric material is greater than 2 nm.
20. The antifuse-integrated VFET of claim 1 , wherein the second dielectric layer directly contacts the first dielectric layer.