Highly regular logic design for efficient 3D integration

1. An integrated circuit comprising:

unit cells arranged in an array, each unit cell comprising:

field effect transistors arranged in a stack;

local interconnect structures comprising select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within the unit cell; and

an array of contacts disposed on an accessible surface of the unit cell, each contact being electrically coupled to a corresponding electrical node of the cell circuitry, wherein:

the unit cells have a common footprint and are positioned in the array so that diffusion breaks embracing the cell circuitry of each unit cell align with the diffusion breaks in adjacent unit cells to form continuous spaces that extend across all unit cells in respective columns of the array, and

the integrated circuit further comprising power walls disposed in the continuous spaces, the power walls providing electrical power to at least the unit cells in the respective columns of the array.

2. The integrated circuit of claim 1 , further comprising a functionalization layer comprising electrically conductive wiring segments formed between select contacts on respective accessible surfaces of one or more unit cells in the array.

3. The integrated circuit of claim 1 , wherein upper surfaces of the power walls are exposed on the accessible surface of each unit cell in the respective columns of the array.

4. The integrated circuit of claim 1 , wherein lower surfaces of the respective power walls are connected to buried power rails.

5. The integrated circuit of claim 1 , wherein the cell circuitry is identical across all unit cells in the array.

6. The integrated circuit of claim 5 , wherein the cell circuitry is constructed from front end-of-line and middle end-of-line structures that extend across the unit cells.

7. The integrated circuit of claim 6 , wherein the front-end of line and middle-end of line processes include multiplication patterning processes.

8. The integrated circuit of claim 7 , wherein the multiplication patterning processes include directed self-assembly and/or self-aligned double patterning.

9. The integrated circuit of claim 1 , wherein the field effect transistors are stacked in complementary pairs.

10. The integrated circuit of claim 9 , wherein gates of each of the complementary pairs of field effect transistors are electrically connected to one another.

11. The integrated circuit of claim 10 , wherein the complementary pairs in the stack of field effect transistors is greater than one in number.

12. The integrated circuit of claim 1 , wherein the field effect transistors are stacked in planes that are parallel to the accessible surface.

13. The integrated circuit of claim 1 , wherein the integrated circuit is monolithic.

14. An integrated circuit comprising:

electrical contacts disposed across a surface beneath which identical unit cells are constructed, each unit cell comprising:

transistors arranged in a stack, and

local interconnect structures comprising select conductive paths between select terminals of the transistors to define cell circuitry that is confined within the unit cell,

wherein select nodes of the cell circuitry are connected to the electrical contacts disposed over the stack of transistors of each unit cell; and

power walls disposed in continuous spaces between groups of the unit cells, the power walls providing electrical power to at least the unit cells in the corresponding group thereof.

15. The integrated circuit of claim 14 , further comprising a functionalization layer including electrically conductive wiring segments formed between select ones of the electrical contacts.

16. The integrated circuit of claim 14 , wherein select ones of the local interconnect structures are connected to at least one of the power walls.

17. The integrated circuit of claim 14 , wherein the transistors are stacked in planes that are parallel to the surface on which the electrical contacts are disposed.