Electronic device including a transistor and a shield electrode
An electronic device can include a substrate, an active region of a transistor, and a shield electrode. The substrate can define a trench and include a mesa adjacent to the trench, and the shield electrode can be within the trench. In an embodiment, the electronic device can further include an active region of a transistor within the mesa and an insulating layer including a thicker section and a thinner section closer to a bottom of the trench. In another embodiment, the electronic device can include a body region and a doped region within the mesa and spaced apart from the body region by a semiconductor region. The doped region can have a dopant concentration that is higher than a dopant concentration of the semiconductor region and a portion of the substrate underlying the doped region.
1. An electronic device comprising:
a substrate including a semiconductor layer and defining a trench extending from a primary surface of the substrate, wherein the substrate includes a mesa adjacent to the trench, and the trench has a lowermost point along a bottom of the trench;
a shield electrode within the trench, wherein the shield electrode has an uppermost point closer to the primary surface of the substrate than to the lowermost point along the bottom of the trench;
an insulating layer including a first section and a second section, wherein:
each of the first section and the second section is disposed between the shield electrode and the mesa,
the first section of the insulating layer has a first thickness,
the second section of the insulating layer has a second thickness,
the bottom of the trench is closer to the first section than to the second section, and
the first thickness is thinner than the second thickness; and
a doped region within the mesa, wherein:
the doped region is disposed between a portion of the mesa above the doped region and a portion of the semiconductor layer underlying the doped region,
the doped region, the portion of the mesa, and the portion of the semiconductor layer have a same conductivity type, and
a dopant concentration of the doped region is higher than a dopant concentration of each of the portion of the mesa and the portion of the semiconductor layer.
2. The electronic device of claim 1 , wherein the doped region is closer to the first section of the insulating layer than to the second section of the insulating layer.
3. The electronic device of claim 1 , further comprising a body region within the active region of the transistor, wherein the portion of the mesa is located between the body region and the doped region.
4. The electronic device of claim 3 , wherein the doped region has a dopant concentration that is at least 1.1 times a dopant concentration of the portion of the mesa located between the body region and the doped region.
5. The electronic device of claim 3 , wherein the doped region has a dopant concentration that is at most 50 times the dopant concentration of the portion of the mesa located between the body region and the doped region.
6. The electronic device of claim 1 , wherein the first thickness of the first section of the insulating layer is at most 0.995 times the second thickness of the second section of the insulating layer.
7. The electronic device of claim 1 , wherein the first thickness of the first section of the insulating layer is at least 0.50 times the second thickness of the second section of the insulating layer.
8. The electronic device of claim 1 , wherein each of the first section of the insulating layer and the shield electrode has a height as measured in a vertical direction, and the height of the first section is at least 5% of the height of the shield electrode.
9. The electronic device of claim 1 , wherein each of the second section of the insulating layer and the shield electrode has a height as measured in a vertical direction, and the height of second section is at most 80% of the height of the shield electrode.
10. The electronic device of claim 1 , wherein the doped region extends across an entire width of the mesa.
11. An electronic device comprising:
a substrate including a semiconductor layer and defining a trench extending from a primary surface of the substrate, wherein the substrate includes a mesa adjacent to the trench;
a shield electrode within the trench;
a body region within the mesa; and
a doped region within the mesa, wherein the doped region is spaced apart from the body region by a semiconductor region; and adjacent to the shield electrode, wherein:
the body region and the doped region are parts of an active region of a transistor,
the doped region is disposed between the semiconductor region and a portion of the semiconductor layer underlying the doped region,
the doped region, the semiconductor region, and the portion of the semiconductor layer have a same conductivity type, and
the doped region has a dopant concentration that is higher than a dopant concentration of each of the semiconductor region and a portion of the semiconductor layer.
12. The electronic device of claim 11 , wherein the dopant concentration of the doped region is at least 2 times higher than the dopant concentration of each of the portion of the mesa and the portion of the semiconductor layer.
13. The electronic device of claim 11 , wherein a dopant concentration of the doped region is at most 50 times higher than the dopant concentration of each of the portion of the mesa and the portion of the semiconductor layer.
14. The electronic device of claim 13 , wherein the doped region is spaced apart from a lowermost point of the trench.
15. A process of forming an electronic device comprising:
patterning a substrate to define a trench extending from a primary surface of the substrate, wherein the substrate includes a mesa adjacent to the trench, and the trench has a sidewall and a lowermost point along a bottom of the trench;
forming a first insulating layer within the trench;
forming a first portion of a shield electrode within the trench;
forming a second insulating layer along the sidewall of the trench after forming the first portion of the shield electrode; and
forming a second portion of the shield electrode within the trench after forming the second.
16. The process of claim 15 , wherein forming the first insulating layer and forming the second insulating layer is performed such that the first insulating layer is thinner than the second insulating layer.
17. The process of claim 15 , further comprising forming a doped region within the mesa, wherein, in a finished device:
the doped region is disposed below a portion of the mesa,
the doped region and the portion of the mesa have a same conductivity type, and
a dopant concentration of the doped region is higher than a dopant concentration of the portion of the mesa.
18. The process of claim 15 , further comprising forming a doped region within the mesa, wherein, in a finished device:
a portion of a semiconductor layer underlies the doped region,
the doped region and the portion of the semiconductor layer have the same conductivity type, and
a dopant concentration of the doped region is higher than a dopant concentration of the portion of the semiconductor layer.
19. The process of claim 17 , wherein the doped region is closer to the first portion of the shield electrode than to the second portion of the shield electrode.
20. The process of claim 15 , wherein:
forming the first portion of the shield electrode comprises:
depositing a first conductive layer; and
etching the first conductive layer to remove the first conductive layer outside the trench and recessing the first conductive layer within the trench; and
forming the second portion of the shield electrode comprises:
depositing a second conductive layer, wherein the second conductive layer contacts the first portion of the shield electrode; and
etching the second conductive layer to remove the second conductive layer outside the trench.