Methods and apparatus for driver calibration
Various embodiments of the present technology may comprise methods and apparatus for driver calibration. The methods and apparatus may comprise various circuits and/or systems to minimize an offset output current (e.g., a drive current) due to an offset voltage in an operational amplifier. The methods and apparatus may comprise a current comparator circuit and a replica circuit that operate in conjunction with each other to monitor the drive current and provide a feedback signal, which is then used to adjust the drive current and improve the accuracy of the drive current.
1. A driver calibration circuit, comprising:
a current comparator circuit configured to generate a threshold current and comprising a first node and a second node;
a controller connected to the second node of the current comparator circuit;
a digital-to-analog converter (DAC) connected to an output terminal of the controller;
an amplifier connected to an output terminal of the DAC;
a driver connected to an output terminal of the amplifier and configured to have a first current; and
a replica circuit connected to: the first node of the current comparator circuit; the output terminal of the amplifier; and the driver;
wherein the replica circuit is configured to have a second current that is proportional to the first current.
2. The driver calibration circuit according to claim 1 , wherein the current comparator circuit comprises a first transistor and a second transistor connected in series with each other.
3. The driver calibration circuit according to claim 2 , wherein: the first node is located between the first transistor and the second transistor; and the second node is located between the second transistor and a third transistor.
4. The driver calibration circuit according to claim 3 , wherein the replica circuit comprises a third transistor comprising: a drain terminal connected to the first node of the current comparator circuit; a source terminal connected to the driver; and a gate terminal connected to the driver and the output terminal of the amplifier.
5. The driver calibration circuit according to claim 4 , wherein: the driver comprises a fourth transistor; a gate terminal of the fourth transistor is connected to the output terminal of the amplifier; and a source terminal of the fourth transistor is connected to the replica circuit.
6. The driver calibration circuit according to claim 1 , wherein the current comparator circuit is configured to generate a comparator output voltage at the second node.
7. The driver calibration circuit according to claim 6 , wherein: the comparator output voltage is HIGH if the second current is less than the threshold current; and the comparator output voltage is LOW if the second current is greater than the threshold current.
8. The driver calibration circuit according to claim 1 , wherein, when the first current is approximately zero amperes, a drain voltage of a drive transistor of the driver is approximately equal to a supply voltage.
9. The driver calibration circuit according to claim 1 , wherein the second current is directly proportional to the first current.
10. A system, comprising:
an actuator; and
a control circuit configured to control the actuator and comprising:
a current comparator configured to generate a threshold current and comprising a first node and a second node;
a controller connected to the second node of the current comparator;
a digital-to-analog converter (DAC) connected to an output terminal of the controller;
an amplifier connected to an output terminal of the DAC;
a driver connected to an output terminal of the amplifier and configured to have a first current; and
a replica circuit connected to the first node of the current comparator, the output terminal of the amplifier; and the driver;
wherein the replica circuit is configured to have a second current that is proportional to the first current.
11. The system according to claim 10 , wherein the second current is directly proportional to the first current.
12. The system according to claim 10 , wherein: the first node is located between a first transistor and a second transistor; and the second node is located between the second transistor and a third transistor.
13. The system according to claim 12 , wherein the replica circuit comprises a third transistor comprising: a drain terminal connected to the first node of the current comparator;
a source terminal connected to the driver; and a gate terminal connected to the driver and the output terminal of the amplifier.
14. The system according to claim 13 , wherein: the driver comprises a fourth transistor; a gate terminal of the fourth transistor is connected to the output terminal of the amplifier; and a source terminal of the fourth transistor is connected to the replica circuit.
15. The system according to claim 10 , wherein the current comparator is configured to generate a comparator output voltage at the second node.
16. The system according to claim 15 , wherein: the comparator output voltage is HIGH if the second current is less than the threshold current; and the comparator output voltage is LOW if the second current is greater than the threshold current.
17. The system according to claim 10 , wherein, when the first current is approximately zero amperes, a drain voltage of a drive transistor of the driver is approximately equal to a supply voltage.
18. A driver calibration circuit, comprising:
a current comparator configured to generate a threshold current and comprising a first node and a second node;
a controller connected to the second node of the current comparator;
a digital-to-analog converter (DAC) connected to an output terminal of the controller;
an amplifier connected to an output terminal of the DAC;
a driver connected to an output terminal of the amplifier and configured to have a first current; and
a replica circuit connected to the first node of the current comparator, the output terminal of the amplifier, and the driver;
wherein the replica circuit is configured to have a second current that is directly proportional to the first current.
19. The driver calibration circuit according to claim 18 , wherein: the first node is located between a first transistor and a second transistor; and the second node is located between the second transistor and a third transistor.
20. The driver calibration circuit according to claim 18 , wherein the current comparator is configured to generate a comparator output voltage at the second node.