Reducing RC delay in semiconductor devices

1. A structure, comprising:

a substrate with a first transistor and a second transistor formed thereon, wherein the first and second transistors have an equal height and each comprises source/drain regions and a gate structure;

a local interconnect layer comprising source/drain contacts and gate contacts respectively connected to the source/drain regions and the gate structure of the first and second transistors, wherein the source/drain contacts are taller than the gate structures of the first and second transistors;

a first interconnect layer on the local interconnect layer and comprising metal lines connected to the source/drain contacts and the gate contacts of the local interconnect layer; and

an air-gap extending into the local interconnect layer and below a top surface of the gate structure and into the first interconnect layer.

2. The structure of claim 1 , further comprising a second interconnect layer on the first interconnect layer with the air-gap extending into the second interconnect layer.

3. The structure of claim 1 , further comprising:

a second interconnect layer on the first interconnect layer; and

a third interconnect layer on the second interconnect layer, wherein the air-gap extends into the second interconnect layer and into the third interconnect layer.

4. The structure of claim 1 , wherein the air-gap occupies between about 30% and about 70% of an area between the source/drain contacts over the first transistor and below the first interconnect layer.

5. The structure of claim 1 , wherein the air-gap occupies between about 40% and about 90% of an area between the metal lines of the first interconnect layer.

6. The structure of claim 1 , wherein the air-gap comprises a liner covering inner sidewall surfaces of the air-gap within the local interconnect layer and the first interconnect layer.

7. The structure of claim 6 , wherein the liner comprises one or more dielectric layers comprising silicon nitride, silicon carbide, or a combination thereof.

8. The structure of claim 1 , wherein the gate contacts are between about 0.25 and about 1.5 times a height of the gate structures of the first and second transistors.

9. The structure of claim 1 , wherein each of the source/drain contacts is shorter than about 2.5 times a height of the gate structures of the first and second transistors.

10. A structure, comprising:

a substrate with a transistor structure formed thereon, wherein the transistor structure comprises source/drain regions and a gate structure;

a local interconnect layer comprising source/drain contacts connected to the source/drain regions of the transistor structure;

a first interconnect layer disposed on the local interconnect layer and comprising metal lines connected to the source/drain contacts of the local interconnect layer; and

an air-gap in the first interconnect layer, wherein the air-gap is positioned above the transistor structure, extends between neighboring metal lines of the first interconnect layer, and comprises a liner layer covering inner sidewall surfaces of the air-gap within the first interconnect layer.

11. The structure of claim 10 , further comprising a second interconnect layer disposed on the first interconnect layer, wherein a portion of the air-gap extends from the first interconnect layer into the second interconnect layer.

12. The structure of claim 11 , wherein the portion of the air-gap extending from the first interconnect layer into the second interconnect layer occupies an area less than about 40% of an area between metal lines of the second interconnect layer.

13. The structure of claim 11 , wherein the portion of the air-gap extending from the first interconnect layer into the second interconnect layer has a rounded top surface surrounded by a dielectric material of the second interconnect layer.

14. The structure of claim 10 , wherein the source/drain contacts have heights that are between about 1.0 and about 2.5 times that of the gate structure.

15. The structure of claim 11 , wherein the liner layer extends into an etch stop layer between the first interconnect layer and the second interconnect layer.

16. A structure, comprising:

a transistor structure on a substrate, wherein the transistor structure comprises source/drain regions disposed in the substrate and a gate structure;

a first dielectric layer on the substrate, wherein the transistor structure is embedded in the first dielectric layer;

source/drain contacts within the first dielectric layer and on the source/drain regions of the transistor structure;

a second dielectric layer on the first dielectric layer;

metal lines in the second dielectric layer, wherein the metal lines are connected to the source/drain contacts;

an air-gap in the first and second dielectric layers, wherein the air-gap comprises an opening in the second dielectric layer between the metal lines and in the first dielectric layer between the source/drain contacts and extending below a top surface of the gate structure; and

a third dielectric layer on the air-gap.

17. The structure of claim 16 , wherein the source/drain contacts comprise a height between about 1.0 and about 2.5 times that of the gate structure.

18. The structure of claim 16 , further comprising a liner in contact with internal surfaces of the air-gap.

19. The structure of claim 16 , wherein a top portion of the opening is between about 25% and about 30% of a distance between the metal lines.

20. The structure of claim 10 , wherein the local interconnect layer comprises a gate contact connected to the gate structure and the gate contact is between about 0.25 and about 1.5 times a height of the gate structure.