Imaging systems and methods for performing pixel binning and variable integration for analog domain regional feature extraction
Imaging circuitry may include circuits for implementing feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using variable charge integration times, variable resistors in the readout path, and/or variable switch on times in the readout path. The weighted pixels values may be binned and combined to obtain an output neuron voltage for at least one layer in a neural network. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.
1. Imaging circuitry, comprising:
a first pixel configured to generate a first weighted pixel value using a first integration time;
a second pixel configured to generate a second weighted pixel value using a second integration time that is different than the first integration time;
an output circuit configured to combine the first and second weighted pixel values to generate a corresponding analog output voltage;
a first set of switches that couple the first pixel to the output circuit; and
a second set of switches that couple the second pixel to the output circuit, wherein the first and second pixels are formed on a first die, and wherein the first and second sets of switches and the output circuit are formed on a second die.
2. The imaging circuitry of claim 1 , wherein the first and second pixels are formed in the same row in an array of pixels.
3. The imaging circuitry of claim 1 , wherein the first pixel comprises a first charge transfer switch controlled by a first control signal, wherein the second pixel comprises a second charge transfer switch controlled by a second control signal, and wherein the first and second control signals are pulsed at different times.
4. The imaging circuitry of claim 1 , further comprising:
a third pixel configured to generate a third weighted pixel value using a third integration time that is different than the first and second integration times.
5. The imaging circuitry of claim 1 , wherein the first die is stacked on top of the second die.
6. The imaging circuitry of claim 1 , further comprising:
a first resistor coupled in series with the first set of switches; and
a second resistor coupled in series with the second set of switches.
7. The imaging circuitry of claim 1 , further comprising:
a first variable resistor that is coupled in series with the first set of switches and that is configured to fine tune the first weighted pixel value; and
a second variable resistor that is coupled in series with the second set of switches and that is configured to fine tune the second weighted pixel value.
8. The imaging circuitry of claim 1 , wherein at least one of the first set of switches is turned on for a first adjustable duration to fine tune the first weighted pixel value, and wherein at least one of the second set of switches is turned on for a second adjustable duration to fine tune the second weighted pixel value.
9. The imaging circuitry of claim 1 , wherein the first pixel comprises:
a floating diffusion region;
a dual conversion gain switch; and
a fixed capacitor coupled to the floating diffusion region via the dual conversion gain switch, wherein the fixed capacitor is configured to store a previously accumulated charge for transferring to the floating diffusion region through the dual conversion gain switch.
10. The imaging circuitry of claim 1 , wherein the first pixel comprises:
a floating diffusion region;
a dual conversion gain switch; and
a variable capacitor coupled to the floating diffusion region via the dual conversion gain switch, wherein the variable capacitor is configured to fine tune the first weighted pixel value.
11. The imaging circuitry of claim 1 , wherein the first weighted pixel value comprises a positive weighted pixel value, wherein the second weighted pixel value comprises a negative weighted pixel value, and wherein the output circuit is configured to compute a difference between the positive and negative weighted pixel values.
12. The imaging circuitry of claim 1 , wherein the first pixel has a first reset drain terminal, wherein the second pixel has a second reset drain terminal that is shorted to the first reset drain terminal, and wherein the first reset drain terminal is selectively coupled to a first additional pixel via a horizontal binning switch or to a second additional pixel via a vertical binning switch.
13. Imaging circuitry, comprising:
a first group of pixels each that are interconnected via first reset transistor drain terminals and that are formed in a first die; and
a second group of pixels that are interconnected via second reset transistor drain terminals and that are formed in the first die, wherein the first group of pixels is selectively coupled to the second group of pixels via a binning switch linking the first and second reset transistor drain terminals, and wherein the binning switch is shared among each pixel in at least the first group of pixels and is formed in a second die that is different than the first die.
14. The imaging circuitry of claim 13 , wherein at least a first pixel in the first group of pixels is configured to generate a first weighted pixel value using a first integration time, and wherein at least a second pixel in the second group of pixels is configured to generate a second weighted pixel value using a second integration time different than the first integration time.
15. The imaging circuitry of claim 13 , wherein the first die is stacked on top of the second die.
16. The imaging circuitry of claim 13 , wherein the first group of pixels are each coupled to a first set of switches via first source follower drain terminals, and wherein the second group of pixels are each coupled to a second set of switches via second source follower drain terminals.
17. The imaging circuitry of claim 16 , wherein the first and second sets of switches are formed in the second die.