Low pin count reversible scan architecture

1. A circuit, comprising:

a plurality of scan chains configured to perform scan shifting in two opposite directions; and

a register configured to store a first signal, the first signal determining whether the plurality of scan chains operate in a first mode or a second mode, wherein the plurality of scan chains operating in the first mode is configured to perform, based on a second signal, either scan shifting in a first direction in the two opposite directions or scan capturing during a test, and wherein the plurality of scan chains operating in the second mode is configured to perform, based on the second signal, scan shifting in the first direction or a second direction in the two opposite directions.

2. The circuit recited in claim 1 being a circuit block in a large circuit.

3. The circuit recited in claim 2 , wherein the first signal is delivered to the register through a network conforming to IEEE 1687-2014 (IJTAG).

4. The circuit recited in claim 2 , wherein the second signal is generated by circuitry in the large circuit.

5. The circuit recited in claim 4 , wherein the circuitry generates the second signal based on signals from a TAP (Test Access Port) controller.

6. The circuit recited in claim 1 , wherein the first signal is delivered to the register through a data streaming mechanism before conducting a test.

7. The circuit recited in claim 1 , wherein the second signal is generated by a tester while conducting a test.

8. The circuit recited in claim 1 , wherein the plurality of scan chains comprising bidirection scan cells.

9. The circuit recited in claim 1 , further comprising:

a signal processing circuit configured to generate a scan enable signal and a scan directional signal based on the first signal and the second signal, the scan enable signal determining whether the plurality of scan chains perform scan shifting or scan capturing during a test, the scan directional signal determining whether the plurality of scan chains perform scan shifting in the first direction or the second direction.

10. The circuit recited in claim 9 , wherein the signal processing circuit comprises:

an AND gate having the first signal and the second signal as inputs and having the scan enable signal as an output; and

an OR gate having the first signal and the second signal as inputs and having the scan directional signal as an output.

11. One or more non-transitory computer-readable media storing computer-executable instructions for causing a computer to perform a method for creating test circuitry in a circuit design for testing a chip fabricated according to the circuit design, the test circuitry comprising:

a plurality of scan chains configured to perform scan shifting in two opposite directions; and

a register configured to store a first signal, the first signal determining whether the plurality of scan chains operate in a first mode or a second mode, wherein the plurality of scan chains operating in the first mode is configured to perform, based on a second signal, either scan shifting in a first direction in the two opposite directions or scan capturing during a test, and wherein the plurality of scan chains operating in the second mode is configured to perform, based on the second signal, scan shifting in the first direction or a second direction in the two opposite directions.

12. The one or more non-transitory computer-readable media recited in claim 11 , wherein the test circuitry is in a circuit block in the circuit design.

13. The one or more non-transitory computer-readable media recited in claim 12 , wherein the first signal is delivered to the register through a network conforming to IEEE 1687-2014 (IJTAG).

14. The one or more non-transitory computer-readable media recited in claim 12 , the second signal is generated by circuitry in the circuit design.

15. The one or more non-transitory computer-readable media recited in claim 14 , wherein the circuitry generates the second signal based on signals from a TAP (Test Access Port) controller.

16. The one or more non-transitory computer-readable media recited in claim 11 , wherein the first signal is delivered to the register through a data streaming mechanism before conducting a test.

17. The one or more non-transitory computer-readable media recited in claim 11 , wherein the second signal is generated by a tester while conducting a test.

18. The one or more non-transitory computer-readable media recited in claim 11 , wherein the plurality of scan chains comprising bidirection scan cells.

19. The one or more non-transitory computer-readable media recited in claim 11 , wherein the test circuitry further comprises:

a signal processing circuit configured to generate a scan enable signal and a scan directional signal based on the first signal and the second signal, the scan enable signal determining whether the plurality of scan chains perform scan shifting or scan capturing during a test, the scan directional signal determining whether the plurality of scan chains perform scan shifting in the first direction or the second direction.

20. The one or more non-transitory computer-readable media recited in claim 19 , wherein the signal processing circuit comprises:

an AND gate having the first signal and the second signal as inputs and having the scan enable signal as an output; and

an OR gate having the first signal and the second signal as inputs and having the scan directional signal as an output.