Partial chain reconfiguration for test time reduction
According to an embodiment, a first aspect relates to a method for testing a scan chain. The method includes segmenting the scan chain into two or more segments; adding a respective multiplexer at end points of each segment, wherein each pair of sequential segment shares a common multiplexer in between; asserting a select signal at a select terminal of the multiplexers such that a relative position of the two or more segments is rearranged positionally in a rearranged scan chain; generating a test pattern to be communicated to an input terminal of the rearranged scan chain and observing a test result at an output of the rearranged scan chain; and determining a fault condition in the rearranged scan chain based on comparing the test result and an expected result.
1. A method for testing a scan chain, the method comprising:
segmenting the scan chain into two or more segments;
adding a respective multiplexer at end points of each segment, wherein each pair of sequential segment shares a common multiplexer in between;
asserting a select signal at a select terminal of the multiplexers such that a relative position of the two or more segments is rearranged positionally in a rearranged scan chain;
generating a test pattern to be communicated to an input terminal of the rearranged scan chain and observing a test result at an output of the rearranged scan chain; and
determining a fault condition in the rearranged scan chain based on comparing the test result and an expected result.
2. The method of claim 1 , wherein the scan chain is segmented into a first segment and a second segment sequential to each other, and wherein, in the rearranged scan chain, a position of the first segment sequentially follows a position of the second segment.
3. The method of claim 2 , wherein the first segment and the second segment are of equal length.
4. The method of claim 1 , wherein the scan chain is a first scan chain, the method further comprising retaining an original configuration of a second scan chain adjacent to the first scan chain in response to the first scan chain being rearranged.
5. The method of claim 4 , wherein the select signal is a first select signal, the method further comprising:
segmenting a third scan chain adjacent to the second scan chain into two or more segments;
adding a multiplexer at end points of each segment of the third scan chain, wherein each sequential segment of the third scan chain shares a common multiplexer in between;
asserting a second select signal at a select terminal of the one or more multiplexers in the third scan chain such that a relative position of the two or more segments of the third scan chain are rearranged positionally in a rearranged third scan chain;
generating a second test pattern to be communicated to an input terminal of the rearranged third scan chain and observing a test result at an output of the rearranged third scan chain; and
determining a fault condition in the rearranged third scan chain based on a comparison between the test result and an expected result for the rearranged third scan chain.
6. The method of claim 5 , wherein the first select signal and the second select signal are the same select signal and asserted at a common test point register.
7. The method of claim 5 , wherein the first scan chain, the second scan chain, and the third scan chain share a common compression circuit, a common decompression circuit, a common combinational logic, or a combination thereof.
8. A scan chain, comprising:
a plurality of sequential segments; and
a plurality of multiplexers, each multiplexer arranged at end points of each segment, wherein each pair of sequential segment shares a common multiplexer in between, each multiplexer configured to receive a select signal such that a relative position of each sequential segment is rearranged positionally in a rearranged scan chain,
wherein a test pattern is fed to an input terminal of the rearranged scan chain and a test result is observed at an output of the rearranged scan chain, and
wherein a fault condition is determined in the rearranged scan chain based on a comparison between the test result and an expected result.
9. The scan chain of claim 8 , wherein the scan chain is segmented into a first segment and a second segment sequential to each other, and wherein, in the rearranged scan chain, a position of the first segment sequentially follows a position of the second segment.
10. The scan chain of claim 9 , wherein the first segment and the second segment are of equal length.
11. The scan chain of claim 9 , wherein a first input terminal of a first multiplexer is configured to receive a test pattern, a second input terminal of the first multiplexer is configured to receive an output signal from the second segment, and an output terminal of the first multiplexer is fed to the first segment, wherein a first input terminal of a second multiplexer is configured to receive an output signal from the first segment, a second input terminal of the second multiplexer is configured to receive a test pattern, and an output terminal of the second multiplexer is fed to the second segment, and wherein a first input terminal of a third multiplexer is configured to receive an output signal from the first segment, a second input terminal of the third multiplexer is configured to receive an output signal from the second segment, and an output terminal of the third multiplexer is observed to determine the fault condition.
12. The scan chain of claim 8 , wherein the scan chain is a first scan chain, and wherein a second scan chain adjacent to the first scan chain retains an original configuration in response to the first scan chain being rearranged.
13. The scan chain of claim 12 , wherein the select signal is a first select signal, wherein a third scan chain shares a common compression circuit, a common decompression circuit, a common combinational logic, or a combination thereof, with the first scan chain and the second scan chain, and wherein the third scan chain comprises:
a second plurality of sequential segments; and
a second plurality of multiplexers, each multiplexer in the second plurality of multiplexers is arranged at end points of each segment in the second plurality of sequential segments, wherein each pair of sequential segments in the second plurality of sequential segments shares a common multiplexer in between, each multiplexer in the second plurality of multiplexers is configured to receive a second select signal such that a relative position of each sequential segment in the second plurality of sequential segments is rearranged positionally in a second rearranged scan chain,
wherein a second test pattern is fed to an input terminal of the second rearranged scan chain and a second test result is observed at an output of the second rearranged scan chain, and
wherein a second fault condition is determined in the second rearranged scan chain based on a comparison between the second test result and a second expected result.
14. The scan chain of claim 13 , wherein the first select signal and the second select signal are the same select signal and asserted at a common test point register.
15. A test system, comprising:
a plurality of scan chains, wherein each alternate scan chain in the plurality of scan chains comprises:
a plurality of sequential segments, and
a plurality of multiplexers, each multiplexer arranged at end points of each segment, wherein each pair of sequential segment shares a common multiplexer in between, each multiplexer configured to receive a select signal such that a relative position of each sequential segment is rearranged positionally in a rearranged scan chain,
wherein a test pattern is fed to an input terminal of the rearranged scan chain and a test result is observed at an output of the rearranged scan chain, and
wherein a fault condition is determined in the rearranged scan chain based on a comparison between the test result and an expected result.
16. The test system of claim 15 , further comprising a compression circuit, a decompression circuit, and a combinational logic, wherein the scan chains in the plurality of scan chains are configured to receive a test signal via the decompression circuit and output a test result via the compression circuit, and wherein two or more scan chains in the plurality of scan chains drive the combinational logic.
17. The test system of claim 16 , wherein, in a non-rearranged configuration of each alternate scan chain, at least one pair of adjacent scan chains drive the common combinational logic at the same shift cycle, and wherein, in the rearranged configuration of each alternate scan chain, the at least one pair of adjacent scan chains drive the common combinational logic at different shift cycles.
18. The test system of claim 15 , wherein each scan chain is segmented into a first segment and a second segment sequential to each other, and wherein, in each rearranged scan chain, a position of an associated first segment sequentially follows a position of an associated second segment.
19. The test system of claim 18 , wherein, in each alternate scan chain, a first input terminal of each first multiplexer is configured to receive a test pattern, a second input terminal of the each first multiplexer is configured to receive an output signal from the second segment, and an output terminal of the each first multiplexer is fed to the first segment, wherein a first input terminal of each second multiplexer is configured to receive an output signal from the first segment, a second input terminal of each second multiplexer is configured to receive a test pattern, and an output terminal of each second multiplexer is fed to the second segment, and wherein a first input terminal of each third multiplexer is configured to receive an output signal from the first segment, a second input terminal of each third multiplexer is configured to receive an output signal from the second segment, and an output terminal of each third multiplexer is observed to determine the fault condition.
20. The test system of claim 15 , wherein a select terminal of each multiplexer is coupled to a common test point register.