Method to embed planar FETs with finFETs
Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
1. A method comprising:
patterning a semiconductor substrate to define a mesa and a fin;
forming a trench isolation structure overlying the semiconductor substrate and surrounding the mesa and the fin;
forming a first gate dielectric layer on the mesa, but not the fin;
recessing the trench isolation structure around the fin after the forming the first gate dielectric layer;
depositing a second gate dielectric layer overlying the first gate dielectric layer at the mesa and further overlying the fin;
forming a first gate electrode overlying the first and second gate dielectric layers at the mesa and partially defining a planar field-effect transistor; and
forming a second gate electrode overlying the second gate dielectric layer at the fin and partially defining a fin field-effect transistor.
2. The method according to claim 1 , wherein the forming of the first gate dielectric layer comprises:
depositing the first gate dielectric layer overlying the fin and the mesa; and
patterning the first gate dielectric layer to remove the first gate dielectric layer from the fin, but not the mesa.
3. The method according to claim 1 , wherein the forming of the first and second gate electrodes comprises:
depositing a gate electrode layer covering the mesa and the fin over the first and second gate dielectric layers; and
performing a selective etch into the gate electrode layer to form the first and second gate electrodes from the gate electrode layer.
4. The method according to claim 1 , further comprising:
performing an etch into the mesa and the fin to simultaneously form a pair of first openings and a pair of second openings, wherein the first openings are formed in the mesa with the first gate electrode sandwiched between the first openings, wherein the second openings are formed in the fin with the second gate electrode sandwiched between the second openings, and wherein the first openings have different profiles than the second openings.
5. The method according to claim 4 , further comprising:
depositing first epitaxial structures and second epitaxial structures respectively in the first and second openings, wherein heights of the first epitaxial structures are smaller than heights of the second epitaxial structures.
6. The method according to claim 1 , further comprising:
recessing a top surface portion of the trench isolation structure at the mesa, but not the fin, until the top surface portion is about even with a top surface of the mesa.
7. A method comprising:
performing a first etch into a semiconductor substrate to form a mesa and a fin;
forming a trench isolation structure overlying the semiconductor substrate and surrounding the mesa and the fin;
depositing a first gate dielectric layer covering the mesa and the fin;
performing a second etch into the first gate dielectric layer and the trench isolation structure while the mesa and a first top surface portion of the trench isolation structure are masked, wherein the second etch exposes the fin and etches back a second top surface portion of the trench isolation structure, and wherein the first and second top surface portions respectively border the mesa and the fin, and further extend in individual closed paths respectively around the mesa and the fin;
depositing a second gate dielectric layer and a gate layer overlying the first gate dielectric layer, the mesa, and the fin; and
performing a third etch into the gate layer to form a first gate and a second gate respectively overlying the mesa and the fin.
8. The method according to claim 7 , wherein the mesa has a large top surface area compared to the fin.
9. The method according to claim 7 , wherein a bottom edge of the first gate is elevated relative to a top edge of the mesa, and wherein a bottom edge of the second gate is recessed relative to a top edge of the fin.
10. The method according to claim 7 , wherein the first gate overlies the first and second gate dielectric layers, wherein the second gate overlies the second gate dielectric layer, and wherein the second gate dielectric layer extends from the second gate to the fin.
11. The method according to claim 7 , wherein the forming of the trench isolation structure comprises:
depositing a dielectric layer covering the semiconductor substrate; and
performing a planarization into the dielectric layer until a top surface of the dielectric layer is level with a top surface of the semiconductor substrate.
12. The method according to claim 7 , further comprising:
performing a fourth etch into the trench isolation structure to reduce a difference in elevation between the first top surface portion of the trench isolation structure and a top surface of the mesa before the depositing of the first gate dielectric layer.
13. The method according to claim 12 , wherein the second top surface portion of the trench isolation structure is masked during the fourth etch.
14. A method comprising:
patterning a semiconductor substrate to form a semiconductor mesa and a semiconductor fin;
forming a trench isolation structure overlying the semiconductor substrate and surrounding the semiconductor mesa and the semiconductor fin, wherein the trench isolation structure covers a sidewall of the semiconductor mesa and a sidewall of the semiconductor fin;
depositing a first gate dielectric layer overlying the semiconductor mesa and the semiconductor fin;
performing a second etch into the trench isolation structure to expose the sidewall of the semiconductor fin, wherein the sidewall of the semiconductor mesa remains covered by the trench isolation structure at completion of the second etch;
depositing a second gate dielectric layer and a gate layer overlying the first gate dielectric layer, the semiconductor mesa, and the semiconductor fin; and
performing a third etch into the gate layer to form a first gate and a second gate respectively overlying the semiconductor mesa and the semiconductor fin, wherein the second gate extends along the sidewall of the semiconductor fin.
15. The method according to claim 14 , wherein the semiconductor mesa has a length that is greater than twice a length of the semiconductor fin, and wherein the semiconductor mesa has a width that is greater than twice a width of the semiconductor fin.
16. The method according to claim 14 , further comprising:
forming a recess in a top surface of the trench isolation structure at the semiconductor mesa, wherein the top surface of the trench isolation structure has a top surface portion that is in the recess, and wherein the top surface portion is level with a top surface of the semiconductor mesa.
17. The method according to claim 16 , wherein the top surface portion extends in a closed path around the semiconductor mesa.
18. The method according to claim 16 , wherein the recess is spaced from the semiconductor fin.
19. The method according to claim 14 , wherein the first gate is farther from a bottom surface of the semiconductor substrate than the second gate.
20. The method according to claim 14 , wherein the first gate dielectric layer is deposited by thermal oxidation.