Communication channel calibration for drift conditions
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
1. A controller to control a memory component, the controller comprising:
circuitry to sample a pattern transmitted from the memory component, according to a sampling phase defined relative to a clock of the controller; and
circuitry to establish a value of the sampling phase during a calibration operation and to adjust the value in response to drift between the sampling phase and timing associated with the pattern transmitted by the memory component, the drift being detected subsequent to establishment of the value.
2. The controller of claim 1 , wherein the circuitry to sample is to sample the pattern from a bidirectional link, wherein the controller further comprises circuitry to transmit data to the memory component via the bidirectional link.
3. The controller of claim 2 , wherein:
the bidirectional link is a differential conductive path;
the circuitry to sample is to receive the pattern as a sequence of symbol from the bidirectional link at a first number of symbols per second;
the controller comprises a set of internal wires which together carry the pattern each at a second number of symbols per second, the second number being less than the first number.
4. The controller of claim 3 , wherein the symbols are bits, wherein the circuitry to sample is to sample the pattern via the differential conductive path at a transmission rate of at least 3200 megabits per second.
5. The controller of claim 1 , wherein the controller further comprises storage to store the pattern, and wherein the circuitry to establish and to adjust is to compare sampled pattern transmitted from the memory component with the pattern in the storage.
6. The controller of claim 5 , wherein the circuitry to establish and to adjust is to generate pass/fail samples from the comparison for respective sampling phases and is to choose the value in dependence on the pass/fail samples for the respective sampling phases.
7. The controller of claim 1 , wherein the controller further comprises circuitry to transmit is to transmit a sequence of digital symbols according to a transmit phase defined relative to the clock, and wherein the controller further comprises circuitry to adjust the transmit phase.
8. The controller of claim 1 , wherein the controller further comprises circuitry to transmit the pattern as part of a write operation directed to addressable memory space within a memory core of the memory component, and wherein the memory component is to retransmit the pattern as part of a read operation.
9. The controller of claim 1 , wherein the circuitry to establish and to adjust the value is to:
establish at least one symbol edge parameter; and
set the value in dependence on the established at least one symbol edge parameter.
10. The controller of claim 1 , wherein the circuitry to establish and to adjust the value is to:
establish the value of the sampling phase in dependence on two symbol edge parameters; and
adjust the value dependent on detected drift in at least one of the two symbol edge parameters.
11. A method of controlling a memory component, comprising, with circuitry:
sampling a pattern transmitted from the memory component, according to a sampling phase defined relative to a clock; and
establishing a value of the sampling phase during a calibration operation and adjusting the value in response to drift between the sampling phase and timing associated with the pattern transmitted by the memory component, the drift being detected subsequent to establishment of the value.
12. The method of claim 11 , wherein sampling comprises sampling the pattern from a bidirectional link, and wherein the method further comprises transmitting data to the memory component via the bidirectional link.
13. The method of claim 12 , wherein:
the bidirectional link is a differential conductive path;
sampling the pattern comprises sampling the pattern from the differential conductive path at a first number of symbols per second
the method further comprises receiving the pattern via a set of internal wires which together carry the pattern each at a second number of symbols per second, less than the first number of symbols per second.
14. The method of claim 13 , wherein the symbols are bits, and wherein sampling further comprises sampling the pattern from the differential conductive path at a rate of at least 3200 megabits per second.
15. The method of claim 11 , further comprising storing the pattern and comparing the pattern transmitted from the memory component with the stored pattern.
16. The method of claim 15 , wherein establishing and adjusting further comprises generating pass/fail samples from the comparison for respective sampling phases and choosing the value in dependence on the pass/fail samples for the respective sampling phases.
17. The method of claim 11 , wherein the method further comprises transmitting data to the memory component as a sequence of digital symbols according to a transmit phase defined relative to the clock, and wherein the method further comprises adjusting the transmit phase.
18. The method of claim 11 , wherein the method further comprises transmitting the pattern to the memory component as part of a write operation directed to addressable memory space within a memory core of the memory component, and wherein the memory component is to retransmit the pattern as part of a read operation.
19. A controller comprising:
circuitry to sample a first pattern transmitted by a memory component, the pattern to be sampled using a sampling clock; and
circuitry to store a value representative of an adjustment to a phase of the sampling clock, wherein the value is established as part of a first calibration operation in which the circuitry to sample is to sample the first pattern;
wherein the value is adjusted in one or more second calibration operations performed based on drift, the one or more second calibration operations being subsequent to the first calibration operation.
20. The controller of claim 19 , wherein the controller further comprises circuitry to detect the drift subsequent to the first calibration operation.