IP Library Patent Application 16861740
Patent Application
App. No. 16/861,740

DIE SUPPORT STRUCTURES AND RELATED METHODS

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
16/861,740
Abstract

Implementations of a semiconductor device may include a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface, and a permanent die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The thickness may be between 0.1 microns and 125 microns. The warpage of the semiconductor die may be less than 200 microns.

Claims (32)

1 . A semiconductor device comprising:

a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and

a permanent die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof;

wherein the thickness is between 0.1 microns and 125 microns; and

wherein a warpage of the semiconductor die is less than 200 microns.

2 . The device of claim 1 , wherein the warpage of the semiconductor die is less than 25 microns.

3 . The device of claim 1 , wherein a perimeter of the semiconductor die is rectangular and a size of the semiconductor die is at least 6 mm by 6 mm.

4 . The device of claim 1 , wherein a perimeter of the semiconductor die is rectangular and a size of the semiconductor die is 211 mm by 211 mm or smaller.

5 . The device of claim 1 , wherein the permanent die support structure comprises a mold compound.

6 . The device of claim 1 , wherein a perimeter of the semiconductor die comprises a closed shape.

7 . The device of claim 1 , wherein the permanent die support structure comprises a perimeter comprising a closed shape.

8 . The device of claim 1 , further comprising a second permanent die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof.

9 . The device of claim 1 , wherein the permanent die support structure comprises two or more layers.

10 . A die support structure comprising:

a material configured to be permanently coupled with a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface;

wherein the material is configured to be coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof; and

wherein the thickness of the semiconductor die is between 0.1 microns and 125 microns.

11 . The die support structure of claim 10 , wherein the material is configured to reduce a warpage of the semiconductor die to less than 200 microns.

12 . The die support structure of claim 10 , wherein the material is a mold compound.

13 . The die support structure of claim 10 , wherein the material is not a polyimide.

14 . The die support structure of claim 10 , wherein the material comprises a perimeter comprising a closed shape.

15 . The die support structure of claim 10 , wherein the material is a first portion of material and further comprising a second portion of material configured to be coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof.

16 . A method of forming a die support structure comprising:

permanently coupling a material with a semiconductor die:

wherein the semiconductor die comprises a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and

wherein the material is coupled with one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof; and

reducing a warpage of the semiconductor die to less than 200 microns through the material.

17 . The method of claim 16 , wherein the material is a mold compound.

18 . The method of claim 16 , wherein the material comprises a perimeter comprising a closed shape.

19 . The method of claim 16 , wherein the material is a first portion of material and further comprising:

permanently coupling a second portion of material with one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof.

20 . The method of claim 19 , wherein the second portion of material is a second layer of material coupled over the first portion of material.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 053613, FRAME 0621 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0942 →
SECURITY INTEREST Recorded Aug 27, 2020
From: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 053613/0621 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2020
From: CARNEY, FRANCIS J.; SEDDON, MICHAEL J.; KUROSE, EIJI; CHEW, CHEE HIONG; WANG, SOON WEI; LIN, YUSHENG
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 052525/0985 →